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Chapter 6 – Section 2 (5/2/04) Page 6.2-8 Miller Compensation of the Two-Stage Op Amp V DD V CC M3 M1 - M2 v in + + VBias - C M M5 M4 V SS Q3 Q4 M6 C M Q6 C c v out C c v out - Q1 Q2 C v I C II in C + I C II M7 + VBias - The various capacitors are: C c = accomplishes the Miller compensation C M = capacitance associated with the first-stage mirror (mirror pole) C I = output capacitance to ground of the first-stage C II = output capacitance to ground of the second-stage Q5 V EE Q7 Fig. 120-08 CMOS Analog Circuit Design © P.E. Allen - 2004 Chapter 6 – Section 2 (5/2/04) Page 6.2-9 Compensated Two-Stage, Small-Signal Frequency Response Model Simplified Use the CMOS op amp to illustrate: 1.) Assume that g m3 >> g ds3 + g ds1 2.) Assume that g m3 C M >> GB Therefore, v 1 v2 C c + -g m1 v in 2 1 g m2 v in C M g m3 2 g m4 v 1 C 1 rds2 ||r ds4 g m6 v 2 r ds6 ||r ds7 C L v out - r ds1 ||r ds3 g m1 v in rds2 ||r ds4 g m6 v 2 rds6 ||r ds7 C II + v in - CI C c v 2 + v out - Fig. 120-09 Same circuit holds for the BJT op amp with different component relationships. CMOS Analog Circuit Design © P.E. Allen - 2004
Chapter 6 – Section 2 (5/2/04) Page 6.2-10 General Two-Stage Frequency Response Analysis + V in - g mI V in C I RI gmII V 2 R II C II where g mI = g m1 = gm2, R I = r ds2 ||r ds4 , C I = C 1 and g mII = g m6 , R II = r ds6 ||r ds7 , C II = C 2 = C L Nodal Equations: -g mI V in = [G I + s(C I + C c )]V 2 - [sC c ]V out and 0 = [g mII - sC c ]V 2 + [G II + sC II + sC c ]V out Solving using Cramer’s rule gives, V out (s) V in (s) = g mI (g mII - sC c ) G I G II +s [G II (C I +C II )+G I (C II +C c )+g mII C c ]+s 2 [C I C II +C c C I +C c C II ] A o [1 - s (C c /g mII )] = 1+s [R I (C I +C II )+R II (C 2 +C c )+g mII R 1 R II C c ]+s 2 [R I R II (C I C II +C c C I +C c C II )] where, A o = g mI g mII R I R II ⎛ ⎞ ⎜ ⎟ In general, D(s) = ⎜1- s p ⎟ ⎜ ⎜ ⎛ 1 ⎝ ⎠ ⎟ ⎟ 1- s ⎞ ⎛ 1 ⎞ ⎜ ⎟ p = 1-s ⎜ ⎟ 2 p + 1 1 p + s2 2 p 1 p → D(s) ≈ 1- s 2 p + s2 1 p 1 p , if |p 2 |>>|p 1 | 2 ∴ p 1 = V 2 C c + ⎝ ⎠ ⎝ V out - Fig.120-10 -1 -1 R I (C I +C II )+R II (C II +C c )+g mII R 1 R II C c ≈ g mII R 1 R II C c , z = g mII C c ⎠ p 2 = -[R I(C I +C II )+R II (C II +C c )+g mII R 1 R II C c ] -g mII C c R I R II (C I C II +C c C I +C c C II ) ≈ C I C II +C c C I +C c C II ≈ -g mII C II , C II > C c > C I CMOS Analog Circuit Design © P.E. Allen - 2004 Chapter 6 – Section 2 (5/2/04) Page 6.2-11 Summary of Results for Miller Compensation of the Two-Stage Op Amp There are three roots of importance: 1.) Right-half plane zero: z 1 = g mII C c = g m6 C c This root is very undesirable- it boosts the magnitude while decreasing the phase. 2.) Dominant left-half plane pole (the Miller pole): -1 p 1 ≈ g mII R I R II C c = -(g ds2+g ds4 )(g ds6 +g ds7 ) g m6 C c This root accomplishes the desired compensation. 3.) Left-half plane output pole: p 2 ≈ -g mII C II ≈ -g m6 C L This pole must be ≥ unity-gainbandwidth or the phase margin will not be satisfied. Root locus plot of the Miller compensation: Closed-loop poles, C c ≠0 Open-loop poles C c =0 jω σ p 2 p 2 ' p 1 ' p 1 z 1 Fig. 120-11 CMOS Analog Circuit Design © P.E. Allen - 2004
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