13.11.2014 Views

chapter 6 - Analog IC Design.org

chapter 6 - Analog IC Design.org

chapter 6 - Analog IC Design.org

SHOW MORE
SHOW LESS

You also want an ePaper? Increase the reach of your titles

YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.

Chapter 6 – Section 1 (5/2/04) Page 6.1-6<br />

Linear and Dynamic Characteristics of the Op Amp<br />

Differential and common-mode frequency response:<br />

⎛V ⎜ 1 (s)+V 2 (s)⎞<br />

⎟<br />

V out (s) = A v (s)[V 1 (s) - V 2 (s)] ± A c (s) ⎜<br />

⎟<br />

⎝ 2 ⎠<br />

Differential-frequency response:<br />

A v0<br />

A v0 p 1 p 2 p 3···<br />

A v (s) =<br />

⎛ s ⎞⎛<br />

s ⎞⎛<br />

s ⎞<br />

= (s -p<br />

⎜ ⎟⎜<br />

⎟⎜<br />

⎟ 1 )(s -p 2 )(s -p 3 )···<br />

⎜ ⎟<br />

⎝p 1<br />

- 1 ⎜ ⎟<br />

⎠⎝p 2<br />

- 1 ⎜ ⎟<br />

⎠⎝p 3<br />

- 1 ···<br />

⎠<br />

where p 1 , p 2 , p 3 ,··· are the poles of the differential-frequency response (ignoring zeros).<br />

20log10(A v0 )<br />

|A v (jω)| dB<br />

Asymptotic<br />

Magnitude<br />

Actual<br />

Magnitude<br />

-6dB/oct.<br />

GB<br />

0dB<br />

Fig. 110-06<br />

ω 1<br />

ω 2 ω 3<br />

ω<br />

-12dB/oct.<br />

-18dB/oct.<br />

CMOS <strong>Analog</strong> Circuit <strong>Design</strong> © P.E. Allen - 2004<br />

Chapter 6 – Section 1 (5/2/04) Page 6.1-7<br />

Other Characteristics of the Op Amp<br />

Power supply rejection ratio (PSRR):<br />

PSRR ∆V DD<br />

= ∆V OUT<br />

A v (s) V o/V in (V dd = 0)<br />

= V o /V dd (V in = 0)<br />

Input common mode range (<strong>IC</strong>MR):<br />

<strong>IC</strong>MR = the voltage range over which the input common-mode signal can vary<br />

without influence the differential performance<br />

Slew rate (SR):<br />

SR = output voltage rate limit of the op amp<br />

Settling time (T s ):<br />

-<br />

+<br />

v OUT<br />

Final Value + ε<br />

Final Value<br />

Final Value - ε<br />

v OUT (t)<br />

ε<br />

ε<br />

Upper Tolerance<br />

Lower Tolerance<br />

Settling Time<br />

0<br />

0<br />

v IN<br />

Fig. 110-07<br />

T s<br />

t<br />

CMOS <strong>Analog</strong> Circuit <strong>Design</strong> © P.E. Allen - 2004

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!