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Chapter 6 – Section 4 (5/2/04) Page 6.4-4 Positive PSRR of the Two-Stage Op Amp - Continued gds6 G II A v0 0 |PSRR+(jω)| dB g ds6 GB G II A v0 GB |p 2 | ω Fig. 180-04 At approximately the dominant pole, the PSRR falls off with a -20dB/decade slope and degrades the higher frequency PSRR + of the two-stage op amp. Using the values of Example 6.3-1 we get: PSRR+(0) = 68.8dB, z 1 = -5MHz, z 2 = -15MHz and p 1 = -906Hz CMOS Analog Circuit Design © P.E. Allen - 2004 Chapter 6 – Section 4 (5/2/04) Page 6.4-5 Concept of the PSRR+ for the Two-Stage Op Amp V dd M3 M4 C c M6 V out V DD C c V out V dd 0dB 1 R out C c ω VBias M1 M5 M2 M7 C II V out V dd Rout Other sources of PSRR+ besides C c C I Fig. 180-05 V SS 1.) The M7 current sink causes V SG6 to act like a battery. 2.) Therefore, V dd couples from the source to gate of M6. 3.) The path to the output is through any capacitance from gate to drain of M6. Conclusion: The Miller capacitor C c couples the positive power supply ripple directly to the output. Must reduce or eliminate C c . CMOS Analog Circuit Design © P.E. Allen - 2004
Chapter 6 – Section 4 (5/2/04) Page 6.4-6 Negative PSRR of the Two-Stage Op Amp withV Bias Grounded M3 M4 C c M6 V out V DD VBias M1 M5 M2 M7 C II V ss C I Fig. 180-06 C c gm7V ss gmIV out R I C I gmIIV 1 C II R II V out - + VBias grounded V SS Nodal equations for V Bias grounded: 0 = (G I + sC c +sC I )V 1 - (g mI +sC c )V o g m7 V ss = (g MII -sC c )V 1 + (G II +sC c +sC II )V o Solving for V out /V ss and inverting gives V ss V out = s 2[C c C I +C I C II +C II C c ]+s[G I (C c +C II )+G II (C c +C I )+C c (g mII −g mI )]+G I G II +g mI g mII [s(C c +C I )+G I ]g m7 CMOS Analog Circuit Design © P.E. Allen - 2004 Chapter 6 – Section 4 (5/2/04) Page 6.4-7 Negative PSRR of the Two-Stage Op Amp withV Bias Grounded - Continued Again using techniques described previously, we may solve for the approximate roots as ⎛sC V ⎜ c ⎞ ⎛s(C ⎟ ⎜ c C I +C I C II +C c C II ) ⎞ ⎟ ss ⎛g ⎜ mI g mII ⎞ PSRR- = V ≅ out ⎜ ⎝ ⎠ ⎟ ⎟ G I g m7 ⎣ ⎢ ⎢⎢⎡ ⎜ ⎟ ⎝g + mI 1 ⎜ ⎟ ⎠ ⎝ g mII C + c 1 ⎠ ⎛s(C ⎜ c +C I ) ⎞ ⎟ ⎦ ⎥⎥⎥⎤ ⎜ ⎟ ⎝ G + I 1 ⎠ This equation can be rewritten approximately as PSRR- = V ss Comments: ⎛ ⎜ V out ≅ ⎝ ⎜ g mI g mII ⎞ ⎠ ⎟ ⎟ PSRR- zeros = PSRR + zeros DC gain ≈ Second-stage gain, sC c sC II g + mI 1 ⎜ ⎝ g + 1 mII ⎛ ⎜ ⎜ ⎝ ⎞ ⎛ ⎟ ⎜ ⎟ ⎠ ⎞ ⎟ ⎟ ⎠ G I g m7 ⎣ ⎢ ⎢⎢⎡ ⎛sC ⎜ c ⎞ ⎟ ⎦ ⎥⎥⎥⎤ ⎜ ⎝ G I + 1 ⎟ ⎠ ⎛ ⎜ = ⎜ ⎝ G II A v0 ⎞ ⎠ ⎟ ⎟ s GB + 1 ⎜ ⎜ ⎛ s |p ⎝ 2 | +1 ⎛ ⎜ ⎝ g m7 ⎣ ⎢⎢⎢⎡ ⎛ ⎜ s ⎞ ⎟ ⎦ ⎥⎥⎥⎤ ⎜ ⎝ ⎞ ⎟ ⎠ g mI GB G I +1 PSRR- pole ≈ (Second-stage gain) x (PSRR+ pole) Assuming the values of Ex. 6.3-1 gives a gain of 23.7 dB and a pole -147 kHz. The dc value of PSRR - is very poor for this case, however, this case can be avoided by correctly implementing V Bias which we consider next. ⎟ ⎠ ⎠ ⎟ ⎟ ⎞ CMOS Analog Circuit Design © P.E. Allen - 2004
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