chapter 6 - Analog IC Design.org

More documents

Recommendations

Info

Chapter 6 – Section 2 (5/2/04) Page 6.2-20 Use of Nulling Resistor to Eliminate the RHP Zero (or turn it into a LHP zero) † C c R z C c R V z I + + Inverting v OUT V in g mI v in C I R V I out High-Gain g mII V I R II C - II - Stage Fig. 430-04 Nodal equations: g mI V in + V I ⎛ sC ⎜ c ⎞ ⎟ R I + sC I V I + ⎜ ⎟ ⎝ 1 + sC c R z (V I − V out ) = 0 ⎠ g mII V I + V o ⎛ ⎜ sC c ⎞ ⎟ R II + sC II V out + ⎜ ⎟ ⎝ 1 + sC c R z (V out − V I ) = 0 ⎠ Solution: V out (s) V in (s) = a{1 − s[(C c/g mII ) − R z C c ]} 1 + bs + cs2 + ds3 where a = gmI g mII R I R II b = (C II + C c )R II + (C I + C c )R I + g mII R I R II C c + R z C c c = [R I R II (C I C II + C c C I + C c C II ) + R z C c (R I C I + R II C II )] d = R I R II R z C I C II C c † W,J. Parrish, "An Ion Implanted CMOS Amplifier for High Performance Active Filters", Ph.D. Dissertation, 1976, Univ. of CA., Santa Barbara. CMOS Analog Circuit Design © P.E. Allen - 2004 Chapter 6 – Section 2 (5/2/04) Page 6.2-21 Use of Nulling Resistor to Eliminate the RHP - Continued If R z is assumed to be less than R I or R II and the poles widely spaced, then the roots of the above transfer function can be approximated as −1 −1 p 1 ≅ (1 + g mII R II )R I C c ≅ g mII R II R I C c −g mII C c p 2 ≅ C I C II + C c C I + C c C II ≅ −g mII C II p 4 = −1 R z C I and 1 z 1 = C c (1/g mII − R z ) Note that the zero can be placed anywhere on the real axis. CMOS Analog Circuit Design © P.E. Allen - 2004
Chapter 6 – Section 2 (5/2/04) Page 6.2-22 Conceptual Illustration of the Nulling Resistor Approach V DD C c R II V out R z Fig. Fig. 430-05 V'' V' M6 The output voltage, V out , can be written as ⎛ ⎞ ⎜ ⎟ -g m6 R II⎝ ⎜R z + 1 ⎡ ⎢ sC c ⎟ ⎠ R -R II II⎣ ⎢ V out = R II + R z + 1 V’ + sC c R II + R z + 1 V” = sC c when V = V’ = V’’. Setting the numerator equal to zero and assuming g m6 = g mII gives, z 1 = 1 C c (1/g mII − R z ) ⎤ ⎥ ⎥ ⎦ g m6 R z + g m6 sC c - 1 R II + R z + 1 sC c V CMOS Analog Circuit Design © P.E. Allen - 2004 Chapter 6 – Section 2 (5/2/04) Page 6.2-23 A Design Procedure that Allows the RHP Zero to Cancel the Output Pole, p 2 We desire that z 1 = p 2 in terms of the previous notation. Therefore, 1 C c (1/g mII − R z ) = −g mII C II The value of R z can be found as -p 4 -p 2 -p 1 z 1 ⎛C ⎜ c + C II ⎞ ⎟ R z = ⎜ ⎟ ⎝ C c (1/g mII ) ⎠ With p 2 canceled, the remaining roots are p 1 and p 4 (the pole due to R z ) . For unity-gain stability, all that is required is that A v (0) |p 4 | > A v (0)|p 1 | = g mII R II R I C c = g mI C c and (1/R z C I ) > (g mI /C c ) = GB Substituting R z into the above inequality and assuming C II >> C c results in g mI C c > g mII C I C II This procedure gives excellent stability for a fixed value of C II (≈ C L ). Unfortunately, as C L changes, p 2 changes and the zero must be readjusted to cancel p 2 . jω σ Fig. 430-06 CMOS Analog Circuit Design © P.E. Allen - 2004
Page 1 and 2: Chapter 6 - Introduction (5/2/04) P
Page 3 and 4: Chapter 6 - Section 1 (5/2/04) Page
Page 17: Chapter 6 - Section 2 (5/2/04) Page
Page 69 and 70:
Chapter 6 - Section 7 (5/2/04) Page
Page 71 and 72:
Page 73 and 74:
Page 75 and 76:
Page 77 and 78:
Page 79:
show all

chapter 6 - Analog IC Design.org

Create successful ePaper yourself

Delete template?

Save as template?