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Chapter 6 – Section 3 (5/2/04) Page 6.3-8 Example 6.3-1 - Design of a Two-Stage Op Amp Using the material and device parameters given in Tables 3.1-1 and 3.1-2, design an amplifier similar to that shown in Fig. 6.3-1 that meets the following specifications. Assume the channel length is to be 1µm and the load capacitor is C L = 10pF. Av > 3000V/V V DD = 2.5V V SS = -2.5V GB = 5MHz SR > 10V/µs 60° phase margin V out range = ±2V ICMR = -1 to 2V P diss ≤ 2mW Solution 1.) The first step is to calculate the minimum value of the compensation capacitor C c , C c > (2.2/10)(10 pF) = 2.2 pF 2.) Choose C c as 3pF. Using the slew-rate specification and C c calculate I 5 . I 5 = (3x10-12)(10x106) = 30 µA 3.) Next calculate (W/L) 3 using ICMR requirements. (W/L) 3 = 30x10-6 (50x10 -6 )[2.5 − 2 − .85 + 0.55] 2 = 15 → (W/L) 3 = (W/L) 4 = 15 CMOS Analog Circuit Design © P.E. Allen - 2004 Chapter 6 – Section 3 (5/2/04) Page 6.3-9 Example 6.3-1 - Continued 4.) Now we can check the value of the mirror pole, p 3 , to make sure that it is in fact greater than 10GB. Assume the C ox = 0.4fF/µm 2 . The mirror pole can be found as p -g m3 - 2K’ p S 3 I 3 3 ≈ 2C gs3 = 2(0.667)W 3 L 3 C ox = 2.81x10 9 (rads/sec) or 448 MHz. Thus, p 3 , is not of concern in this design because p 3 >> 10GB. 5.) The next step in the design is to calculate g m1 to get g m1 = (5x106)(2π)(3x10-12) = 94.25µS Therefore, (W/L) 1 is (W/L) 1 = (W/L) g m1 2 2 = 2K’ N I 1 = (94.25) 2 2·110·15 = 2.79 ≈ 3.0 ⇒ (W/L) 1 = (W/L) 2 = 3 6.) Next calculate V DS5 , V DS5 = (−1) − (−2.5) − 30x10 -6 110x10-6·3 - .85 = 0.35V Using V DS5 calculate (W/L) 5 from the saturation relationship. 2(30x10-6) (W/L) 5 = (110x10-6)(0.35)2 = 4.49 ≈ 4.5 → (W/L) 5 = 4.5 CMOS Analog Circuit Design © P.E. Allen - 2004
Chapter 6 – Section 3 (5/2/04) Page 6.3-10 Example 6.3-1 - Continued 7.) For 60° phase margin, we know that g m6 ≥ 10g m1 ≥ 942.5µS Assuming that g m6 = 942.5µS and knowing that g m4 = 150µS, we calculate (W/L) 6 as (W/L) 6 = 15 942.5x10 -6 (150x10-6) = 94.25 ≈ 94 8.) Calculate I 6 using the small-signal g m expression: (942.5x10-6)2 I 6 = (2)(50x10-6)(94.25) = 94.5µA ≈ 95µA If we calculate (W/L) 6 based on V out (max), the value is approximately 15. Since 94 exceeds the specification and maintains better phase margin, we will stay with (W/L) 6 = 94 and I 6 = 95µA. With I 6 = 95µA the power dissipation is P diss = 5V·(30µA+95µA) = 0.625mW. CMOS Analog Circuit Design © P.E. Allen - 2004 Chapter 6 – Section 3 (5/2/04) Page 6.3-11 Example 6.3-1 - Continued 9.) Finally, calculate (W/L) 7 ⎛95x10-6⎞ (W/L) 7 = 4.5 ⎜ ⎟ ⎝ 30x10-6 = 14.25 ≈ 14 → (W/L) ⎠ 7 = 14 Let us check the V out (min) specification although the W/L of M7 is so large that this is probably not necessary. The value of V out (min) is 2·95 V out (min) = V DS7 (sat) = 110·14 = 0.351V which is less than required. At this point, the first-cut design is complete. 10.) Now check to see that the gain specification has been met (92.45x10-6)(942.5x10-6) A v = 15x10-6(.04 + .05)95x10-6(.04 + .05) = 7,697V/V which exceeds the specifications by a factor of two. .An easy way to achieve more gain would be to increase the W and L values by a factor of two which because of the decreased value of λ would multiply the above gain by a factor of 20. 11.) The final step in the hand design is to establish true electrical widths and lengths based upon ∆L and ∆W variations. In this example ∆L will be due to lateral diffusion only. Unless otherwise noted, ∆W will not be taken into account. All dimensions will be rounded to integer values. Assume that ∆L = 0.2µm. Therefore, we have CMOS Analog Circuit Design © P.E. Allen - 2004
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