chapter 6 - Analog IC Design.org

More documents

Recommendations

Info

Chapter 6 – Section 2 (5/2/04) Page 6.2-32 Slew Rate of a Two-Stage CMOS Op Amp Remember that slew rate occurs when currents flowing in a capacitor become limited and is given as I lim = C dv C dt where v C is the voltage across the capacitor C. - v in >>0 + M3 M1 + VBias - I 5 M4 M2 M5 V DD V SS Positive Slew Rate C c I5 Assume a virtural ground M6 I 6 I CL C L I 7 M7 v out - v in I 5 SR- = min⎢ ⎥ ⎣ C c , I 7-I 5 C L = I 5 ⎦ Cc if I 7 >>I 5 . Therefore, if C L is not too large and if I 7 is significantly greater than I 5 , then the slew rate of the two-stage op amp should be, SR = I 5 Cc v out Chapter 6 – Section 3 (5/2/04) Page 6.3-1 SECTION 6.3 - TWO-STAGE OP AMP DESIGN Unbuffered, Two-Stage CMOS Op Amp V DD M3 M4 C c M6 v out Notation: - M1 M2 v in + + VBias - M5 V SS M7 C L Fig. 6.3-1 S i = W i L i = W/L of the ith transistor CMOS Analog Circuit Design © P.E. Allen - 2004
Chapter 6 – Section 3 (5/2/04) Page 6.3-2 DC Balance Conditions for the Two-Stage Op Amp For best performance, keep all transistors in saturation. M4 is the only transistor that cannot be forced into saturation by internal connections or external voltages. Therefore, we develop conditions to force M4 to - be in saturation. 1.) First assume that V SG4 = V SG6 . This will + cause “proper mirroring” in the M3-M4 mirror. Also, the gate and drain of M4 are at the same potential so that M4 is “guaranteed” to be in saturation. ⎛S ⎜ 6 ⎞ ⎟ 2.) If V SG4 = V SG6 , then I 6 = ⎜ ⎟ ⎝ S 4 I ⎠ 4 ⎛S ⎜ 7 ⎞ ⎛S ⎟ ⎜ 7 ⎞ ⎟ 3.) However, I 7 = ⎜ ⎟ ⎝ S 5 I 5 = ⎜ ⎟ ⎝ S 5 (2I 4 ) ⎠ ⎠ V DD + V + SG4 V SG6 - - M6 M3 M4 I 4 C c I 6 M1 M2 v in I 7 I 5 + M7 VBias M5 - 4.) For balance, I 6 must equal I 7 ⇒ S 6 S 4 = 2S 7 S 5 called the “balance conditions” 5.) So if the balance conditions are satisfied, then V DG4 = 0 and M4 is saturated. CMOS Analog Circuit Design © P.E. Allen - 2004 V SS C L v out Fig. 6.3-1A Chapter 6 – Section 3 (5/2/04) Page 6.3-3 Design Relationships for the Two-Stage Op Amp Slew rate SR I 5 = C c (Assuming I 7 >>I 5 and C L > C c ) g m1 2g m1 First-stage gain A v1 = g ds2 + g = ds4 I 5 (λ 2 + λ 4 ) g m6 g m6 Second-stage gain A v2 = g ds6 + g = ds7 I 6 (λ 6 + λ 7 ) Gain-bandwidth GB g m1 = C c Output pole p −g m6 2 = C L RHP zero z g m6 1 = C c 60° phase margin requires that g m6 = 2.2g m2 (C L /C c ) if all other roots are ≥ 10GB. Positive ICMR V in(max) = V DD − Negative ICMR V in(min) = V SS + I 5 β 3 − |V T03 | (max) + V T1(min) ) I 5 β 1 + V T1(max) + V DS5 (sat) Saturation voltageV DS (sat) = 2I DS β (all transistors are saturated) CMOS Analog Circuit Design © P.E. Allen - 2004
Page 1 and 2: Chapter 6 - Introduction (5/2/04) P
Page 3 and 4: Chapter 6 - Section 1 (5/2/04) Page
Page 23: Chapter 6 - Section 2 (5/2/04) Page
Page 75 and 76:
Chapter 6 - Section 7 (5/2/04) Page
Page 77 and 78:
Page 79:
show all

chapter 6 - Analog IC Design.org

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?