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Chapter 6 – Section 3 (5/2/04) Page 6.3-20<br />
5-to-1 Current Mirror with Different Physical Performances<br />
Input<br />
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1<br />
Poly<br />
Diffusion<br />
Contacts<br />
Ground<br />
Output<br />
; Input<br />
Ground<br />
Figure 6.3-6 The layout of a 5-to-1 current mirror. (a) Layout which minimizes<br />
area at the sacrifice of matching. (b) Layout which optimizes matching.<br />
CMOS <strong>Analog</strong> Circuit <strong>Design</strong> © P.E. Allen - 2004<br />
Chapter 6 – Section 3 (5/2/04) Page 6.3-21<br />
1-to-1.5 Transistor Matching<br />
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2 1 2 1 2<br />
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Drain 2<br />
Gate 2<br />
Source 2<br />
Drain 1<br />
Gate 1<br />
Source 1<br />
Metal 2 Metal 1 Poly Diffusion Contacts<br />
Figure 6.3-7 The layout of two transistors with a 1.5 to 1 matching using<br />
centroid geometry to improve matching.<br />
CMOS <strong>Analog</strong> Circuit <strong>Design</strong> © P.E. Allen - 2004