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Chapter 6 – Section 5 (5/2/04) Page 6.5-4 Two-Stage Op Amp with a Cascoded First-Stage MC3 R M3 MB3 V DD M4 MB4 MC4 v o1 MT2 MT1 C c M6 v out MB5 MC1 + MC2 M1 M2 VBias MB1 MB2 + - vin - v in 2 - + 2 + M5 VBias - V SS CMOS Analog Circuit Design © P.E. Allen - 2004 M7 Fig. 6.5-2 • MT1 and MT2 are required for level shifting from the first-stage to the second. • The PSRR+ is improved by the presence of MT1 p2 • Internal loop pole at the gate of M6 may cause the Miller compensation to fail. • The voltage gain of this op amp could easily be 100,000V/V jω σ p 3 p 1 z 1 Fig. 6.5-2 Chapter 6 – Section 5 (5/2/04) Page 6.5-5 Two-Stage Op Amp with a Cascode Second-Stage V DD M3 M4 R z VBP C c M6 MC6 v out - M1 M2 v in + + VBias - M5 V SS CMOS Analog Circuit Design © P.E. Allen - 2004 VBN MC7 M7 C L Fig. 6.5-3 A v = g mI g mII R I R II where g mI = g m1 = g m2 , g mII = g m6 , 1 2 R I = g ds2 + g ds4 = (λ 2 + λ 4 )I D5 and R II = (g mC6 r dsC6 r ds6 )||(g mC7 r dsC7 r ds7 ) Comments: • The second-stage gain has greatly increased improving the Miller compensation • The overall gain is approximately (g m r ds )3 or very large • Output pole, p 2 , is approximately the same if C c is constant • The zero RHP is the same if C c is constant
Chapter 6 – Section 5 (5/2/04) Page 6.5-6 A Balanced, Two-Stage Op Amp using a Cascode Output Stage V ⎛g ⎜ m1 g m8 v in ⎞ ⎟ v out = ⎜ ⎟ ⎝ g m3 2 + g DD m2g m6 v in g m4 2 R II ⎠ M4 M6 M15 ⎛g ⎞ ⎜ m1 ⎟ = ⎜ ⎟ ⎝ 2 +g m2 M3 M8 2 kv M14 M7 in R II = g m1·k·R II v in - v in M1 M2 + M5 + VBias - V SS R 1 M9 M10 R 2 M13 M12 M11 ⎠ where R II = (g m7 r ds7 r ds6 )||(g m12 r ds12 r ds11 ) and k = g m8 g m3 = g m6 g m4 This op amp is balanced because the drain-to-ground loads for M1 and M2 are identical. TABLE 1 - Design Relationships for Balanced, Cascode Output Stage Op Amp. C L Fig. 6.5-4 v out Slew rate = I out C L GB = g m1g m8 g m3 C L A v = 1 2 ⎜ ⎜ ⎛ g m1 g m8 ⎝ ⎠ ⎟ ⎟ + g m2g m6 ⎞ g m3 g m4 R II V in (max) = V DD − ⎣ ⎢ ⎡I 5 ⎤1/2 ⎥ β 3 ⎦ − |V TO3 |(max) +V T1 (min) ⎡I 5 ⎤ 1/2 V in (min) = V SS + V DS5 + ⎢ ⎥ ⎣ β 1 + V T1 (min) ⎦ CMOS Analog Circuit Design © P.E. Allen - 2004 Chapter 6 – Section 5 (5/2/04) Page 6.5-7 Example 6.5-2 Design of Balanced, Cascoded Output Stage Op Amp The balanced, cascoded output stage op amp is a useful alternative to the two-stage op amp. Its design will be illustrated by this example. The pertinent design equations for the op amp were given above. The specifications of the design are as follows: V DD = −V SS = 2.5 V Slew rate = 5 V/µs with a 50 pF load GB = 10 MHz with a 25 pF load A v ≥ 5000 Input CMR = −1V to +1.5 V Output swing = ±1.5 V Use the parameters of Table 3.1-2 and let all device lengths be 1 µm. Solution While numerous approaches can be taken, we shall follow one based on the above specifications. The steps will be numbered to help illustrate the procedure. 1.) The first step will be to find the maximum source/sink current. This is found from the slew rate. I source /I sink = C L × slew rate = 50 pF(5 V/µs) = 250 µA 2.) Next some W/L constraints based on the maximum output source/sink current are developed. Under dynamic conditions, all of I 5 will flow in M4; thus we can write Max. I out (source) = (S 6 /S 4 )I 5 and Max. I out (sink) = (S 8 /S 3 )I 5 The maximum output sinking current is equal to the maximum output sourcing current if S 3 = S 4 , S 6 = S 8 , and S 10 = S 11 CMOS Analog Circuit Design © P.E. Allen - 2004
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