chapter 6 - Analog IC Design.org

More documents

Recommendations

Info

Chapter 6 – Section 2 (5/2/04) Page 6.2-16 Summary of the Conditions for Stability of the Two-Stage Op Amp • Unity-gainbandwith is given as: ⎛ 1 ⎞ ⎜ ⎟ GB = A v (0)·|p 1 | = (g mI g mII R I R II g ⎟ )·⎝⎜ mII R I R II C c = g mI ⎛ 1 ⎞ ⎜ ⎟ ⎠ C c = (g m1 g m2 R 1 R 2 g ⎟ )·⎝⎜ m2 R 1 R 2 C c = g m1 ⎠ C c • The requirement for 45° phase margin is: ⎛ ω ⎞ ±180° - Arg[AF] = ±180° - tan-1⎜ ⎟ ⎝ |p1| - tan ⎛ ω ⎞ -1⎜ ⎟ ⎠ ⎝ |p2| - tan ⎛ω⎞ -1⎜ ⎟ ⎠ ⎝ z = 45° ⎠ Let ω = GB and assume that z ≥ 10GB, therefore we get, ⎛GB⎞ ±180° - tan-1⎜ ⎟ ⎝ |p1| - tan ⎛GB⎞ -1⎜ ⎟ ⎠ ⎝ |p2| - tan ⎛GB⎞ -1⎜ ⎟ ⎠ ⎝ z = 45° ⎠ ⎛GB⎞ 135° ≈ tan-1(Av(0)) + tan-1⎜ ⎟ ⎝ |p2| + tan ⎛GB⎞ -1(0.1) = 90° + tan-1⎜ ⎟ ⎠ ⎝ |p2| + 5.7° ⎠ ⎛GB⎞ 39.3° ≈ tan-1⎜ ⎟ ⎝ |p2| ⇒ GB ⎠ |p 2 | = 0.818 ⇒ |p 2| ≥ 1.22GB • The requirement for 60° phase margin: |p2| ≥ 2.2GB if z ≥ 10GB • If 60° phase margin is required, then the following relationships apply: gm6 Cc > 10g m1 Cc ⇒ g m6 > 10gm1 and g m6 C2 > 2.2g m1 Cc ⇒ Cc > 0.22C2 CMOS Analog Circuit Design © P.E. Allen - 2004 Chapter 6 – Section 2 (5/2/04) Page 6.2-17 Controlling the Right-Half Plane Zero Why is the RHP zero a problem? Because it boosts the magnitude but lags the phase - the worst possible combination for stability. jω jω 3 θ1 θ 2 jω 2 180° > θ 1 > θ 2 > θ 3 jω 1 θ3 σ Fig. 430-01 Solution of the problem: If a zero is caused by two paths to the output, then eliminate one of the paths. z 1 CMOS Analog Circuit Design © P.E. Allen - 2004
Chapter 6 – Section 2 (5/2/04) Page 6.2-18 Use of Buffer to Eliminate the Feedforward Path through the Miller Capacitor Model: The transfer function is given by the following equation, V o (s) V in (s) = (g mI )(g mII )(R I )(R II ) 1 + s[R I C I + R II C II + R I C c + g mII R I R II C c ] + s2[R I R II C II (C I + C c )] Using the technique as before to approximate p 1 and p 2 results in the following −1 −1 p 1 ≅ R I C I + R II C II + R I C c + g mII R I R II C c ≅ g mII R I R II C c and C c +1 C V c I + + v OUT V in gmI v in C I R I V out g mII V R I II C - II Inverting High-Gain Stage −g mII C c p 2 ≅ C II (C I + C c ) Comments: Poles are approximately what they were before with the zero removed. For 45° phase margin, |p 2 | must be greater than GB For 60° phase margin, |p 2 | must be greater than 1.73GB V out - Fig. 430-02 CMOS Analog Circuit Design © P.E. Allen - 2004 Chapter 6 – Section 2 (5/2/04) Page 6.2-19 Use of Buffer with Finite Output Resistance to Eliminate the RHP Zero Assume that the unity-gain buffer has an output resistance of R o . Model: R o Inverting High-Gain Stage +1 C c C V c I + + v OUT V in gmI v in C I R I R R o o V out g mII V R I II C - II - V out Fig. 430-03 It can be shown that if the output resistance of the buffer amplifier, R o , is not neglected that another pole occurs at, −1 p 4 ≅ R o [C I C c /(C I + C c )] and a LHP zero at z 2 ≅ −1 R o C c Closer examination shows that if a resistor, called a nulling resistor, is placed in series with C c that the RHP zero can be eliminated or moved to the LHP. CMOS Analog Circuit Design © P.E. Allen - 2004
Page 1 and 2: Chapter 6 - Introduction (5/2/04) P
Page 3 and 4: Chapter 6 - Section 1 (5/2/04) Page
Page 15: Chapter 6 - Section 2 (5/2/04) Page
Page 67 and 68:
Chapter 6 - Section 6 (5/2/04) Page
Page 69 and 70:
Page 71 and 72:
Page 73 and 74:
Page 75 and 76:
Page 77 and 78:
Page 79:
show all

chapter 6 - Analog IC Design.org

Create successful ePaper yourself

Delete template?

Save as template?