chapter 6 - Analog IC Design.org

Chapter 6 – Section 4 (5/2/04) Page 6.4-8
Negative PSRR of the Two-Stage Op Amp withV Bias Connected to V SS
M3
M4
C c
M6
V out
V DD
VBias
M1
M5
M2
VBias connected to V SS
M7
C II
V ss
C r ds7
C gd7
c
V ss r ds5
+
+
C I R I V 1 g mII V 1 C II r ds6 Vout
g mI V out
-
-
V SS
C I
Fig. 180-07
If the value of V Bias is independent of V ss , then the model shown results. The nodal
equations for this model are
0 = (G I + sC c + sC I )V 1 - (g mI + sC c )V out
and
(gds7 + sC gd7 )V ss = (g mII - sC c )V 1 + (G II + sC c + sC II + sC gd7 )V out
Again, solving for V out /V ss and inverting gives
V ss
V out
= s 2[C c C I +C I C II +C II C c +C I C gd7 +C c C gd7 ]+s[G I (C c +C II +C gd7 )+G II (C c +C I )+C c (g mII −g mI )]+G I G II +g mI g mII
(sC gd7 +g ds7 )(s(C I +C c )+G I )
CMOS Analog Circuit Design © P.E. Allen - 2004
Chapter 6 – Section 4 (5/2/04) Page 6.4-9
Negative PSRR of the Two-Stage Op Amp withV Bias Connected to V SS - Continued
Assuming that g mII > g mI and solving for the approximate roots of both the numerator
and denominator gives
PSRR- = V ss
⎛
⎜
V out
≅
⎝
⎜
g mI g mII
⎞
⎠
⎟
⎟
This equation can be rewritten as
PSRR- = V ss
⎛
⎜
V out
≈
⎝
⎜
sC c s(C c C I +C I C II +C c C II )
g + mI
1 ⎜ ⎝
g mII C + c
1
⎛
⎜
⎜
⎝
⎞ ⎛
⎟ ⎜
⎟
⎠
G I g ds7
⎣
⎢ ⎢⎢⎡ ⎛sC ⎜ gd7
⎞ ⎛s(C ⎟ ⎜ I +C c ) ⎞
⎟
⎦ ⎥⎥⎥⎤
G II A v0
⎞
⎠
⎟
⎟
⎛
⎜
⎝
⎜
⎝
g ds7
+1
⎝
⎜
g ds7
⎣ ⎢⎢⎢⎡ ⎛sC ⎜ gd7
⎞ ⎛sC ⎟ ⎜ c
⎞
⎟
⎦ ⎥⎥⎥⎤
⎜
⎝
⎞
⎟
⎠
⎟
⎠
s
GB + 1 ⎜ ⎜ ⎛ s
|p
⎝ 2 | +1
g ds7
+1 ⎜ ⎝
G I
+ 1
⎟
⎠
⎠ ⎟ ⎟ ⎞
⎟
⎠
G I
+ 1
Comments:
• DC gain has been increased by the ratio of G II to g ds7
• Two poles instead of one, however the pole at -g ds7 /C gd7 is large and can be ignored.
Using the values of Ex. 6.3-1 and assume that C ds7 = 10fF, gives,
PSRR-(0) = 76.7dB and Poles at -71.2kHz and -149MHz
⎟
⎠
⎞
⎟
⎟
⎠
CMOS Analog Circuit Design © P.E. Allen - 2004