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Chapter 6 – Section 3 (5/2/04) Page 6.3-16 Example 6.3-2 - Continued It is worthwhile to check that the RHP zero has been moved on top of p 2 . To do this, first calculate the value of R z . V SG8 must first be determined. It is equal to V SG10 , which is V SG10 = 2I 10 K’ P S 10 + |V TP | = 2·15 50·1 + 0.7 = 1.474V Next determine R z . 1 R z = K’ P S 8 (V SG10 -|V TP |) = 106 50·5.63(1.474-.7) = 4.590kΩ The location of z 1 is calculated as −1 z 1 = (4.590 x 103)(3x10 -12 ) − The output pole, p 2 , is 3x10 -12 = -94.46x106 rads/sec 942.5x10 -6 p 2 = 942.5x10 -6 10x10 -12 = -94.25x10 6 rads/sec Thus, we see that for all practical purposes, the output pole is canceled by the zero that has been moved from the RHP to the LHP. The results of this design are summarized below. W 8 = 6 µm W 9 = 2 µm W 10 = 1 µm W 11 = 15 µm CMOS Analog Circuit Design © P.E. Allen - 2004 Chapter 6 – Section 3 (5/2/04) Page 6.3-17 An Alternate Form of Nulling Resistor To cancel p 2 , z 1 = p 2 → R z = C c+C L 1 g m6A C = C g m6B Which gives ⎛ ⎜ g m6B = g m6A⎝ ⎜ C c ⎞ ⎟ ⎟ ⎠ C c +C L In the previous example, g m6A = 942.5µS, C c = 3pF and C L = 10pF. Choose I 6B = 10µA to get or g m6B = g m6AC c C c + C L → W 6B L 6B ⎛ = ⎜ ⎝ 3 ⎞ ⎟ ⎠ I 13 2 6A W 6A I 6B L 6A ⎛ = ⎜ ⎝ 2K P W 6B I 6B L 6B - M1 M2 v in + + VBias - M3 M4 M5 V DD M11 M6B M8 V SS M10 C c M9 M6 v out C L M7 Fig. 6.3-4A 3 ⎞ ⎟ 13 2 ⎛ ⎜ ⎠ ⎝ ⎟ ⎠ ⎛ = ⎜ ⎝ C c C c +C L ⎞ ⎟ ⎠ 2K P W 6A I D6 L 6A 95⎞ 10 (94) = 47.6 → W 6B = 48µm CMOS Analog Circuit Design © P.E. Allen - 2004
Chapter 6 – Section 3 (5/2/04) Page 6.3-18 Programmability of the Two-Stage Op Amp The following relationships depend on the bias current, I bias , in the following manner and allow for programmability after fabrication. A v (0) = g mI g mII R I R II ∝ 1 I Bias GB = g mI C ∝ I Bias c P diss = (V DD +|V SS |)(1+K 1 +K 2 )I Bias ∝ I bias SR = K 1I Bias C c ∝ I Bias 1 R out = 2λK 2 I Bias ∝ 1 I Bias 1 |p 1 | = g mII R I R II C c ∝ I Bias 2 I ∝ I 1.5 Bias Bias |z| = g mII C c ∝ I Bias Illustration of the I bias dependence → 103 102 101 100 P diss and SR - v in M1 M2 + IBias K 1 IBias K 2IBias CMOS Analog Circuit Design © P.E. Allen - 2004 |p 1 | GB and z M3 10-1 Ao and R out 10-2 10-3 1 10 100 I Bias Fig. 160-05 I Bias (ref) V DD M4 M5 V SS M6 M7 v out Fig. 6.3-04D Chapter 6 – Section 3 (5/2/04) Page 6.3-19 Simulation of the Electrical Design Area of source or drain = AS = AD = W[L1 + L2 + L3] where L1 = Minimum allowable distance between the contact in the S/D and the polysilicon (5µm) L2 = Width of a minimum size contact (5µm) L3 = Minimum allowable distance from contact in S/D to edge of S/D (5µm) ∴ AS = AD = Wx15µm Perimeter of the source or drain = PD = PS = 2W + 2(L1+L2+L3) ∴ PD = PS = 2W + 30µm Illustration: L3 L2 L1 L1 L2 L3 Poly W Diffusion Diffusion L Fig. 6.3-5 CMOS Analog Circuit Design © P.E. Allen - 2004
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