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Chapter 6 – Section 5 (5/2/04) Page 6.5-12 Technological Implications of the Cascode Configuration A A B C D B C D Thin oxide ;Poly I II n+ n-channel n+ p substrate/well ;;; Fig. 6.5-5 ;; ;; If a double poly CMOS process is available, internode parasitics can be minimized. As an alternative, one should keep the drain/source between the transistors to a minimum area. B C A D Minimum Poly A separation B C D Thin oxide Poly I Poly I n+ n-channel n+ n-channel n+ p substrate/well ;;;;;; Fig. 6.5-5A CMOS Analog Circuit Design © P.E. Allen - 2004 Chapter 6 – Section 5 (5/2/04) Page 6.5-13 Input Common Mode Range for Two Types of Differential Amplifier Loads V DD -V SD3 +V TN V DD V DD V DD -V SG3 +V TN + + + + V SG3 V SD4 V SD3 V SD4 Input Input - M3 M4 - Common - M3 M4 - Common Mode VBP Mode Range Range M1 M2 M1 M2 V SS +V DS5 +V GS1 + VBias - M5 v icm V SS V SS +V DS5 +V GS1 + VBias - V SS M5 v icm Differential amplifier with Differential amplifier with a current mirror load. current source loads. Fig. 6.5-6 In order to improve the ICMR, it is desirable to use current source (sink) loads without losing half the gain. The resulting solution is the folded cascode op amp. CMOS Analog Circuit Design © P.E. Allen - 2004
Chapter 6 – Section 5 (5/2/04) Page 6.5-14 The Folded Cascode Op Amp V DD I I M14 M4 I 4 M5 I 5 I 3 M8 M9 A B R A R B + 1 2 M13 M6 I 6 M7 M1 M2 R 1 I7 v in - R 2 M3 M12 M10 M11 + VBias - V SS Fig. 6.5-7 Comments: • I 4 and I 5 , should be designed so that I 6 and I 7 never become zero (i.e. I 4 =I 5 =1.5I 3 ) • This amplifier is nearly balanced (would be exactly if R A was equal to R B ) • Self compensating • Poor noise performance, the gain occurs at the output so all intermediate transistors contribute to the noise along with the input transistors. (Some first stage gain can be achieved if R A and R B are greater than g m1 or g m2 . CMOS Analog Circuit Design © P.E. Allen - 2004 C L v out Chapter 6 – Section 5 (5/2/04) Page 6.5-15 Small-Signal Analysis of the Folded Cascode Op Amp Model: g m6 v gs6 Recalling what we R A learned about the - resistance looking into g m1 v in r 2 r the source of the ds1 r ds6 ds4 R 2 + 1 + g m10 cascode transistor; R A = r ds6+R 2 +(1/g m10 ) 1 1 + g m6 r ≈ ds6 g and R m6 B = r ds7 + R II R II 1 + g m7 r ≈ ds7 g m7 r where R ds7 II ≈g m9 r ds9 r ds11 The small-signal voltage transfer function can be found as follows. The current i 10 is written as i 10 = -g m1(r ds1 ||r ds4 )v in -g m1v in 2[R A + (r ds1 ||r ds4 )] ≈ 2 and the current i 7 can be expressed as g m2 (r ds2 ||r ds5 )v in g m2 v in i 7 = 2 R = ⎢⎡ II ⎢ ⎣ g m7 r + (r ds7 ds2 ||r ds5 ) ⎦ ⎥⎥⎤ 2 ⎜⎛ ⎜1 + R II(g ds2 +g ds5 ) = g m2v in 2(1+k) where k = R II(g ds2 +g ds5 ) g m7 r ds7 ⎝ g m7 r ds7 ⎠ ⎟⎟⎞ The output voltage, v out , is equal to the sum of i 7 and i 10 flowing through R out . Thus, v out v in = ⎝ ⎜ ⎜⎛ g m1 2 + g m2 2(1+k) R out = ⎜ ⎛ 2+k ⎝ 2+2k g mIR out ⎠ ⎟⎟⎞ ⎠ ⎟⎞ g m7 v gs7 R B i 7 i 10 - + g m2 v v in gs6 r 2 r ds2 r v gs7 ds7 ds5 i 10 v out + R II - Fig. 140-07 CMOS Analog Circuit Design © P.E. Allen - 2004
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