chapter 6 - Analog IC Design.org

Chapter 6 – Section 2 (5/2/04) Page 6.2-12
Compensated Open-Loop Frequency Response of the Two-Stage Op Amp
|A(jω)F(jω)|
A vd (0) dB
Compensated
Uncompensated
-20dB/decade
Arg[-A(jω)F(jω)|
Note that the unity-gainbandwidth, GB, is
GB
0dB
log 10 (ω)
Phase Shift
Uncompensated
-40dB/decade
180°
135°
-45°/decade
90°
-45°/decade
Compensated
45°
Phase
No phase margin
Margin
0°
log 10 (ω)
|p 1 | |p 1 '| |p 2 '| |p 2 |
Fig. 120-12
1
GB = A vd (0)·|p 1 | = (g mI g mII R I R II ) g mII R I R II C = g mI
c C = g m1
c C = g m2
c C c
CMOS Analog Circuit Design © P.E. Allen - 2004
Chapter 6 – Section 2 (5/2/04) Page 6.2-13
Conceptually, where do these roots come from?
1.) The Miller pole:
V DD
|p 1 | ≈
1
R I (g m6 R II C c )
R I
C c
R II
v out
M6
v I
≈g m6 R II C c
Fig. 120-13
2.) The left-half plane output pole:
V DD
|p 2 | ≈ g m6
C II
C c
R II
v out
M6
C II
1
GB·C
≈ 0 c
V DD
R II
v out
M6
C II
3.) Right-half plane zero (One source of zeros is from
multiple paths from the input to output):
g
-g
v out = ⎜ ⎜⎛ m6 R II (1/sC c ) R -R ⎜⎛ m6
II⎝ ⎜
⎝
R
⎠ ⎟⎟⎞
II + 1/sC c
v’ + ⎜ ⎜⎛ II
sC
⎠ ⎟⎟⎞ c
- 1
⎝
R
⎠ ⎟⎟⎞
II + 1/sC c
v’’ = R II + 1/sC c
v
where v = v’ = v’’.
v''
v'
C c
Fig. 120-14
V DD
R II
v out
M6
Fig. 120-15
CMOS Analog Circuit Design © P.E. Allen - 2004