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Chapter 6 – Section 3 (5/2/04) Page 6.3-4 Op Amp Specifications The following design procedure assumes that specifications for the following parameters are given. 1. Gain at dc, A v (0) 2. Gain-bandwidth, GB 3. Phase margin (or settling time) 4. Input common-mode range, ICMR 5. Load Capacitance, C L 6. Slew-rate, SR - 7. Output voltage swing + 8. Power dissipation, P diss Max. ICMR and/or p 3 V DD + V V + V out (max) SG4 SG6 - - M6 g m6 or M3 M4 C c I 6 Proper Mirroring V SG4 =V SG6 GB = g m1 C c v out C v L in C M1 M2 c ≈ 0.2C L (PM = 60°) Min. ICMR I 5 I5 = SR·C c V out (min) + VBias - M5 V SS M7 Fig. 160-02 CMOS Analog Circuit Design © P.E. Allen - 2004 Chapter 6 – Section 3 (5/2/04) Page 6.3-5 Unbuffered Op Amp Design Procedure This design procedure assumes that the gain at dc (A v ), unity gain bandwidth (GB), input common mode range (V in (min) and V in (max)), load capacitance (C L ), slew rate (SR), settling time (T s ), output voltage swing (V out (max) and V out (min)), and power dissipation (P diss ) are given. Choose the smallest device length which will keep the channel modulation parameter constant and give good matching for current mirrors. 1. From the desired phase margin, choose the minimum value for C c , i.e. for a 60° phase margin we use the following relationship. This assumes that z ≥ 10GB. C c > 0.22C L 2. Determine the minimum value for the “tail current” (I 5 ) from the largest of the two values. I 5 = SR .C c or I 5 ≅ 10⎜ ⎛ V DD + |V SS | ⎝ 2 . ⎠ ⎟⎞ Ts 3. Design for S 3 from the maximum input voltage specification. I 5 S 3 = K' 3 [V DD − V in (max) − |V T03 |(max) + V T1 (min)]2 4. Verify that the pole of M3 due to C gs3 and C gs4 (= 0.67W 3 L 3 C ox ) will not be dominant by assuming it to be greater than 10 GB g m3 2C gs3 > 10GB. CMOS Analog Circuit Design © P.E. Allen - 2004
Chapter 6 – Section 3 (5/2/04) Page 6.3-6 Unbuffered Op Amp Design Procedure - Continued 5. Design for S 1 (S 2 ) to achieve the desired GB. g m1 = GB . C c → S g m2 2 2 = K' 2 I 5 6. Design for S 5 from the minimum input voltage. First calculate V DS5 (sat) then find S 5 . V DS5 (sat) = V in (min) − V SS − I 5 2I 5 β 1 −V T1 (max) ≥ 100 mV → S 5 = K' 5 [V DS5 (sat)]2 7. Find S 6 by letting the second pole (p 2 ) be equal to 2.2 times GB and assuming that V SG4 = V SG6 . g m6 = 2.2g m2 (C L /C c ) and g m6 2K P 'S 6 I 6 S 6 I 6 g m4 = = 2K P 'S 4 I 4 S 4 I 4 = S 6 S 4 → S 6 = g m6 g m4 S 4 8. Calculate I 6 from I g m6 2 6 = 2K' 6 S 6 Check to make sure that S 6 satisfies the V out (max) requirement and adjust as necessary. 9. Design S 7 to achieve the desired current ratios between I 5 and I 6 . S 7 = (I 6 /I 5 )S 5 (Check the minimum output voltage requirements) CMOS Analog Circuit Design © P.E. Allen - 2004 Chapter 6 – Section 3 (5/2/04) Page 6.3-7 Unbuffered Op Amp Design Procedure - Continued 10. Check gain and power dissipation specifications. 2g m2 g m6 A v = I 5 (λ 2 + λ 3 )I 6 (λ 6 + λ 7 ) P diss = (I 5 + I 6 )(V DD + |V SS |) 11. If the gain specification is not met, then the currents, I 5 and I 6 , can be decreased or the W/L ratios of M2 and/or M6 increased. The previous calculations must be rechecked to insure that they are satisfied. If the power dissipation is too high, then one can only reduce the currents I 5 and I 6 . Reduction of currents will probably necessitate increase of some of the W/L ratios in order to satisfy input and output swings. 12. Simulate the circuit to check to see that all specifications are met. CMOS Analog Circuit Design © P.E. Allen - 2004
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chapter 6 - Analog IC Design.org

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