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Experiment Proposal - opera - Infn

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A complete system has been designed to test the M64 PMT’s (its schematic is given in Section 4.4.3).<br />

The front end electronics of this system is a two stage circuit (Fig. 164). The first one uses the differential<br />

amplifier AD8138 which provides a fixed gain of 4, while the second stage has an adjustable gain of up<br />

to 5 and a buffer (BUF601) which transmits the signal to the ADC. Between the two stages, a splitting<br />

system can also provide an output for an electronic discriminator.<br />

Stage 1 Stage 2<br />

from PMT<br />

AD8138<br />

OPA660<br />

BUF601<br />

to ADC<br />

50 ohms<br />

Gain = 5<br />

Gain = 1 to 4<br />

to discriminator<br />

Figure 164: Schematic view of the front end electronics used for the PMT tests.<br />

Acquisition Rack<br />

RIO2 (1)<br />

CAENET<br />

CBD (2)<br />

VME crate<br />

PC<br />

Linux<br />

Ethernet<br />

ADC (3)<br />

ADC (3)<br />

ADC (3)<br />

Controller<br />

CAMAC crate<br />

Test<br />

system<br />

Poste de travail<br />

Ampli (4)<br />

Ampli (4)<br />

Ampli (4)<br />

Gate - Trig<br />

HV<br />

NIM crate<br />

Analog signals<br />

PMT<br />

x<br />

Control -Trigger &<br />

High Voltage<br />

y<br />

(1) : CES VME processor card (RIO2 8062) based on PowerPC 604e<br />

(2) : CBD (CAMAC Branch Driver)<br />

(3) : ADC Lecroy 2249 W<br />

(4) : Amplifier card developed at IReS<br />

Figure 165: Schematic view of the acquisition system used for the PMT tests.<br />

The charge measurement is done by a Lecroy CAMAC ADC 2249W. The data readout and the<br />

setup of the acquisition is controlled by a VME processor and a VME CBD (Fig. 165). The data flow,<br />

data recording and run control are managed by the CASCADE software [92]. The processor controls the<br />

221

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