Experiment Proposal - opera - Infn

The fast shaper has a high gain in order to trigger on a single photoelectron and to reduce the spread
between different channels when triggering on low levels. This shaper is followed by a comparator with
common adjustable voltage threshold. The 16 outputs of the comparator are ORed together to provide a
common trigger for all the channels. A mask gives the possibility to disable given channels. Simulations
predict a voltage gain of 20 in the fast shaper, 40 ns for the shaping time and the 1 p.e. peak at 4 − 5
σ from the pedestal.
The slow shaper line measures the charge of the signal. The maximum is stored on a capacitance cell
with a hold command generated by the autotrigger. All 16 channels are then read through a multiplexer
implemented on the chip. The following characteristics are expected: shaper gain of 1.2, linearity over
300 p.e (5% non linearity for the whole channel), peaking time of 600 ns, S/Nratioof∼ 10 for 1 p.e.
This HPD chip is expected to be soon available. In parallel, a similar chip is being designed for PMT’s.
We are also testing commercially available chips for the readout of the HPD’s. A large number of
front end chips is suitable for the silicon detectors with various gains, peaking times, noise levels. Among
them the Viking family [60] of IDE AS, 15 originally developped at CERN, offers adequate performance.
The readout sequence of the slow shaper (called VA) starts with a hold signal depending on the
trigger. Each channel holds the signal at the time it received the hold. The delay between trigger and
hold matches the peaking time of the VA (∼ 2 µs). The chip is then clocked and an ADC sampling is
performed until all channels have been read out. The VA chips can host up to 128 channels. We have
tested HPD’s front end boards with two 32 channels VA (VA32c).
Various types of external triggers can be used for the VA. We adopt the TA chip which is directly
bonded to the output of the preamplifier of each VA channel. The TA contains a very fast shaper with
peaking time of 75 ns followed by a comparator. A voltage threshold is set for each channel. The working
principle and the timing sequence of a VA-TA combination are displayed in Fig. 52.
The nominal gain and noise performance of the VA32c (TA32c) are 150 mV/fC and 450 e − ENC
(15 mV/fC and 750 e − ENC). These quantities can be measured in a calibration mode. For a typical
HPD signal of 3500 e − /p.e., corresponding to a charge of 0.57 fC/p.e., one obtains a signal/noise
ratio of ∼ 6 on the charge measurement for a single photoelectron. The details on the test results and
performance of the VA-TA are given in Section 8.2.5.
As an ultimate solution for the front end electronics we are designing an Ethernet capable front end
card. Indeed, the relatively low data rate (∼ 50 Hz in average) 16 allows the direct connection of the
sensors to the event building network through a compact, autonomous, low power and low cost front end
module.
A general block diagram of such a device is shown in Fig. 53. The card contains an analogue front
end, followed by a high speed ADC. A programmable logic device (FPGA) is dedicated to the control of
the readout, the time stamping and communication with the Ethernet device. A FIFO is used for data
buffering.
15 IDE AS, Veritasveien 9, 1322 Hovik, Norway.
16 The exact rate is under evaluation. The Ethernet solution allows a comfortable safety factor of ∼ 40.
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