Experiment Proposal - opera - Infn

Adjustable
gain
Channel 0
Sample & hold
Multiplexer
Discri
To ADC
Channel 63
Discri
Control Logic
Channel address
OR discri
Figure 68: Front end chip diagram.
The number of channels handled by this chip should be adapted to the configuration of each detector.
In the following, the assumption of a channel grouping by 64 is made. Its setup can be done by a serial
link (JTAG or custom protocol). The peaking time (< 1 µs) should be short enough to avoid pileup and
random hits.
The ADC’s have at least 12 bits to reach the required accuracy and dynamic range and are operated
at high frequency (> 1 MHz) to reduce the chip readout time.
The local trigger receives two inputs, the logical discriminator signal from the front end chip and an
optional hardware external trigger (see above). It generates a discriminator information to the readout
interface.
The serial link controller manages the serial link between the front end units and the readout interface
(VME board). The link must be able to accept the maximum estimated rate. In the case of 64 channels,
60 Hz of counting rate and 3 byte per event, the rate is 64 × 60 × 3 = 11520 byte/s.
A daisy chain serial link can be used for some front end units to reduce cabling. If one chains 4
modules together (Fig. 69 for scintillator strips) the above rate is to be multiplied by the same factor
in the last link. Keeping a margin factor of 10 leads to 0.5 Mbyte/s. The wire length is less than
40 m, which is the maximum distance between a front end unit and the associated readout interface.
The RS485 standard could be a good solution (differential link, rate up to 1 Mbyte/s on 50 m). No
processors are needed to handle the transmission protocol. Its logic control can be integrated in the Field
Programmable Gate Array (FPGA), as shown in Fig. 67.
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