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Intel 80310 I/O Processor Chipset AAU Coding Techniques

Intel 80310 I/O Processor Chipset AAU Coding Techniques

Intel 80310 I/O Processor Chipset AAU Coding Techniques

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<strong>Intel</strong> ® <strong>80310</strong> I/O <strong>Processor</strong> <strong>Chipset</strong> <strong>AAU</strong> <strong>Coding</strong> <strong>Techniques</strong>Low-Level Design DocumentTable 7.A software descriptor is created to encapsulate each <strong>AAU</strong> hardware descriptor. The softwaredescriptor contains additional information and status about the hardware descriptor that is notdescribed by the hardware descriptor. The software descriptor also enables the use of stack andqueue data structures to keep track of and manipulate the hardware descriptors without making anyformat changes to the hardware descriptor. A pool of software descriptors are allocated duringinitialization and put on a stack. An equal amount of hardware descriptors are created andencapsulated by the software descriptors. The resource pool removes the performance penaltysuffered by dynamically allocating descriptors during operation.The Table 7 data structure describes the <strong>AAU</strong> software descriptor.<strong>AAU</strong> Software Descriptor Structuretypedef struct _sw_aau_t{aau_desc_t aau_desc; /* <strong>AAU</strong> HW desc */u32 status ; /* <strong>AAU</strong> Status */struct _aau_sgl *next; /* pointer to next sgl */void *dest ; /* Destination */void *src[4] ; /* Source */void *ext_src[4]; /* Extended Source */u32 total_src; /* total src addresses */struct list_head link; /* link to queue */u32 aau_phys; /* <strong>AAU</strong> Physical Addr */u32 desc_addr; /* HW unaligned addr */u32 sgl_head; /* User SGL head Addr */struct _sw_aau_t *head; /* Head of list */struct _sw_aau_t *tail; /* Tail of list */} sw_aau_t;The <strong>AAU</strong> shall also have a global device descriptor that allows access to the accelerator registers,processing queues, queue locks, and accelerator status.White Paper 13

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