Intel 80310 I/O Processor Chipset AAU Coding Techniques

Intel ® 80310 I/O Processor Chipset AAU Coding TechniquesMMU Functions for Intel ® XScale Microarchitectureteq r2, #0mcrnep15, 0, ip, c7, c5, 0@ Invalidate I cache & BTBmcr p15, 0, ip, c7, c10, 4@ Drain Write (& Fill) Buffermov pc, lr/** cpu_xscale_cache_clean_invalidate_range(start, end, flags)** clean and invalidate all cache lines associated with this area of memory** start: Area start address* end: Area end address* flags: nonzero for I cache as well*/.align5ENTRY(cpu_xscale_cache_clean_invalidate_range)bic r0, r0, #CACHELINESIZE - 1@ round down to cache linesub r3, r1, r0cmp r3, #MAX_AREA_SIZEbhi cpu_xscale_cache_clean_invalidate_all_r21: mcr p15, 0, r0, c7, c10, 1@ Clean D cache linemcr p15, 0, r0, c7, c6, 1@ Invalidate D cache lineadd r0, r0, #CACHELINESIZEcmp r0, r1blo 1bteq r2, #0mcr p15, 0, ip, c7, c10, 4@ Drain Write (& Fill) Buffermoveqpc, lrsub r0, r0, r31: mcr p15, 0, r0, c7, c5, 1@ Invalidate I cache lineadd r0, r0, #CACHELINESIZEcmp r0, r1blo 1bmcr p15, 0, ip, c7, c5, 6@ Invalidate BTB80 White Paper