Intel 80310 I/O Processor Chipset AAU Coding Techniques

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Intel ® 80310 I/O Processor Chipset AAU Coding TechniquesAAU Source CodeA.2 Private Definitions for Intel ® XScale MicroarchitectureAAU: \src\aau.h105 /*106 * Private Definitions for Intel ® XScale microarchitecture AAU107 *108 * Author: Dave Jiang (dave.jiang@intel.com)109 * Copyright (C) 2001 Intel Corporation110 *111 * This program is free software; you can redistribute it and/or modify112 * it under the terms of the GNU General Public License version 2 as113 * published by the Free Software Foundation.114 *115 */116117 #ifndef _AAU_PRIVATE_H_118 #define _AAU_PRIVATE_H_119120 #define SLEEP_TIME 50121 #define AAU_DESC_SIZE 48122 #define AAU_INT_MASK 0x0020123124 #define AAU_ACR_CLEAR 0x00000000125 #define AAU_ACR_ENABLE 0x00000001126 #define AAU_ACR_CHAIN_RESUME 0x00000002127 #define AAU_ACR_512_BUFFER 0x00000004128129 #define AAU_ASR_CLEAR 0x00000320130 #define AAU_ASR_MA_ABORT 0x00000020131 #define AAU_ASR_ERROR_MASK AAU_ASR_MA_ABORT132 #define AAU_ASR_DONE_EOT 0x00000200133 #define AAU_ASR_DONE_EOC 0x00000100134 #define AAU_ASR_DONE_MASK (AAU_ASR_DONE_EOT | AAU_ASR_DONE_EOC)135 #define AAU_ASR_ACTIVE 0x0000040036 White Paper
Intel ® 80310 I/O Processor Chipset AAU Coding TechniquesAAU Source Code136 #define AAU_ASR_MASK (AAU_ASR_ERROR_MASK | AAU_ASR_DONE_MASK)137138 /* software descriptor */139 typedef struct _sw_aau140 {141 aau_desc_t aau_desc;/* AAU HW Desc */142 u32 status;143 struct _aau_sgl *next; /* pointer to next SG */144 void *dest; /* destination addr */145 void *src[AAU_SAR_GROUP];/* source addr[4] */146 void *ext_src[AAU_SAR_GROUP];/* ext src addr[4] */147 u32 total_src; /* total number of source */148 struct list_head link; /* Link to queue */149 u32 aau_phys; /* AAU Phys Addr (aligned) */150 u32 desc_addr; /* unaligned HWDESC virtual addr */151 u32 sgl_head;152 struct _sw_aau *head; /* head of list */153 struct _sw_aau *tail; /* tail of list */154 } sw_aau_t;155156 /* AAU registers */157 typedef struct _aau_regs_t158 {159 volatile u32 ACR; /* Accelerator Control Register */160 volatile u32 ASR; /* Accelerator Status Register */161 volatile u32 ADAR; /* Descriptor Address Register */162 volatile u32 ANDAR; /* Next Desc Address Register */163 volatile u32 LSAR[AAU_SAR_GROUP];/* source addrs */164 volatile u32 LDAR; /* local destination address register */165 volatile u32 ABCR; /* byte count */166 volatile u32 ADCR; /* Descriptor Control */167 volatile u32 LSARE[AAU_SAR_GROUP];/* extended src addrs */168 } aau_regs_t;169White Paper 37
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