Intel 80310 I/O Processor Chipset AAU Coding Techniques
Intel 80310 I/O Processor Chipset AAU Coding Techniques
Intel 80310 I/O Processor Chipset AAU Coding Techniques
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<strong>Intel</strong> ® <strong>80310</strong> I/O <strong>Processor</strong> <strong>Chipset</strong> <strong>AAU</strong> <strong>Coding</strong> <strong>Techniques</strong><strong>AAU</strong> Source Code902 list_add_tail(&sw_desc->link, &free_stack);903 spin_unlock_irq(&free_lock);904 }905906 /* set the register data structure to the mapped memory regs <strong>AAU</strong> */907 aau_dev.regs = (aau_regs_t *) IOP310_<strong>AAU</strong>ACR;908909 atomic_set(&aau_dev.ref_count, 0);910911 /* init process Q */912 INIT_LIST_HEAD(&aau_dev.process_q);913 /* init holding Q */914 INIT_LIST_HEAD(&aau_dev.hold_q);915 /* init locks for Qs */916 spin_lock_init(&aau_dev.hold_lock);917 spin_lock_init(&aau_dev.process_lock);918919 aau_dev.last_aau = NULL;920921 /* initialize BH task */922 aau_dev.aau_task.sync = 0;923 aau_dev.aau_task.routine = (void *)aau_task;924925 /* initialize wait Q */926 init_waitqueue_head(&aau_dev.wait_q);927928 /* clear <strong>AAU</strong> channel control register */929 *(IOP310_<strong>AAU</strong>ACR) = <strong>AAU</strong>_ACR_CLEAR;930 *(IOP310_<strong>AAU</strong>ASR) = <strong>AAU</strong>_ASR_CLEAR;931 *(IOP310_<strong>AAU</strong>ANDAR) = 0;932933 /* set default irq threshold */934 atomic_set(&aau_dev.irq_thresh, DEFAULT_<strong>AAU</strong>_IRQ_THRESH);935 DPRINTK("Done!\n");60 White Paper
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