Intel 80310 I/O Processor Chipset AAU Coding Techniques

Intel ® 80310 I/O Processor Chipset AAU Coding TechniquesMMU Functions for Intel ® XScale Microarchitecturebic r0, r0, #(PAGESIZE - 1) & 0x00ffbic r0, r0, #(PAGESIZE - 1) & 0xff00mcr p15, 0, ip, c7, c10, 4@ Drain Write (& Fill) Buffer1: mcr p15, 0, r0, c8, c6, 1@ invalidate D TLB entrymcr p15, 0, r0, c8, c5, 1@ invalidate I TLB entryadd r0, r0, #PAGESIZEcmp r0, r1blo 1bcpwait_ret lr, ip/** cpu_xscale_tlb_invalidate_page(page, flags)** invalidate the TLB entries for the specified page.** page: page to invalidate* flags: non-zero if we include the I TLB*/.align5ENTRY(cpu_xscale_tlb_invalidate_page)mcr p15, 0, ip, c7, c10, 4@ Drain Write (& Fill) Bufferteq r1, #0mcr p15, 0, r0, c8, c6, 1@ invalidate D TLB entrymcrnep15, 0, r3, c8, c5, 1@ invalidate I TLB entrycpwait_ret lr, ip/* ================================ TLB LOCKING==============================** The Intel ® XScale microarchitecture implements support for locking entries into* the Instruction and Data TLBs. The following functions provide the* low level support for supporting these under Linux. xscale-lock.c* implements some higher level management code. Most of the following* is taken straight out of the Developer's Manual.*/White Paper 89