Intel 80310 I/O Processor Chipset AAU Coding Techniques

Intel ® 80310 I/O Processor Chipset AAU Coding TechniquesMMU Functions for Intel ® XScale MicroarchitectureENTRY(cpu_xscale_dcache_invalidate_range)mrc p15, 0, r2, c0, c0, 0@ Read part no.eor r2, r2, #0x69000000eor r2, r2, #0x00052000@ 80200 XX part no.bicsr2, r2, #0x1@ Clear LSB in revision fieldmoveqr2, #0beq cpu_xscale_cache_clean_invalidate_range@ An 80200 A0 or A1tst r0, #CACHELINESIZE - 1mcrnep15, 0, r0, c7, c10, 1@ Clean D cache linetst r1, #CACHELINESIZE - 1mcrnep15, 0, r1, c7, c10, 1@ Clean D cache linebic r0, r0, #CACHELINESIZE - 1@ round down to cache line1: mcr p15, 0, r0, c7, c6, 1@ Invalidate D cache lineadd r0, r0, #CACHELINESIZEcmp r0, r1blo 1bmov pc, lr/** cpu_xscale_dcache_clean_range(start, end)** For the specified virtual address range, ensure that all caches contain* clean data, such that peripheral accesses to the physical RAM fetch* correct data.** start: virtual start address* end: virtual end address*/.align5ENTRY(cpu_xscale_dcache_clean_range)bic r0, r0, #CACHELINESIZE - 1sub r2, r1, r0cmp r2, #MAX_AREA_SIZE82 White Paper