Intel 80310 I/O Processor Chipset AAU Coding Techniques
Intel 80310 I/O Processor Chipset AAU Coding Techniques
Intel 80310 I/O Processor Chipset AAU Coding Techniques
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<strong>Intel</strong> ® <strong>80310</strong> I/O <strong>Processor</strong> <strong>Chipset</strong> <strong>AAU</strong> <strong>Coding</strong> <strong>Techniques</strong>MMU Functions for <strong>Intel</strong> ® XScale Microarchitecture/** This macro is used to wait for a CP15 write and is needed* when we have to ensure that the last operation to the co-pro* was completed before continuing with operation.*/.macrocpwait, rdmrc p15, 0, \rd, c2, c0, 0@ arbitrary read of cp15mov \rd, \rd@ wait for completionsub pc, pc, #4 @ flush instruction pipeline.endm.macrocpwait_ret, lr, rdmrc p15, 0, \rd, c2, c0, 0@ arbitrary read of cp15sub pc, \lr, \rd, LSR #32@ wait for completion and@ flush instruction pipeline.endm/** This macro cleans the entire dcache using line allocate.* The main loop has been unrolled to reduce loop overhead.* rd and rs are two scratch registers.*/.macroclean_d_cache, rd, rsldr \rs, =clean_addrldr \rd, [\rs]eor \rd, \rd, #CACHESIZEstr \rd, [\rs]add \rs, \rd, #CACHESIZE1: mcr p15, 0, \rd, c7, c2, 5@ allocate D cache lineadd \rd, \rd, #CACHELINESIZEmcr p15, 0, \rd, c7, c2, 5@ allocate D cache lineadd \rd, \rd, #CACHELINESIZEmcr p15, 0, \rd, c7, c2, 5@ allocate D cache lineWhite Paper 75