Intel 80310 I/O Processor Chipset AAU Coding Techniques
Intel 80310 I/O Processor Chipset AAU Coding Techniques
Intel 80310 I/O Processor Chipset AAU Coding Techniques
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<strong>Intel</strong> ® <strong>80310</strong> I/O <strong>Processor</strong> <strong>Chipset</strong> <strong>AAU</strong> <strong>Coding</strong> <strong>Techniques</strong>MMU Functions for <strong>Intel</strong> ® XScale Microarchitecturebic r0, r0, #CACHELINESIZE - 11: mcr p15, 0, r0, c7, c10, 1@ Clean D cache linemcr p15, 0, r0, c7, c5, 1@ Invalidate I cache lineadd r0, r0, #CACHELINESIZEcmp r0, r1blo 1bmcr p15, 0, ip, c7, c5, 6@ Invalidate BTBmcr p15, 0, ip, c7, c10, 4@ Drain Write (& Fill) Buffermov pc, lr/** cpu_xscale_icache_invalidate_page(page)** invalidate all Icache lines associated with this area of memory** page: page to invalidate*/.align5ENTRY(cpu_xscale_icache_invalidate_page)mov r1, #PAGESIZE1: mcr p15, 0, r0, c7, c5, 1@ Invalidate I cache lineadd r0, r0, #CACHELINESIZEmcr p15, 0, r0, c7, c5, 1@ Invalidate I cache lineadd r0, r0, #CACHELINESIZEmcr p15, 0, r0, c7, c5, 1@ Invalidate I cache lineadd r0, r0, #CACHELINESIZEmcr p15, 0, r0, c7, c5, 1@ Invalidate I cache lineadd r0, r0, #CACHELINESIZEsubsr1, r1, #4 * CACHELINESIZEbne 1bmcr p15, 0, r0, c7, c5, 6@ Invalidate BTBmov pc, lr/* ================================ CACHE LOCKING============================White Paper 85
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