Intel 80310 I/O Processor Chipset AAU Coding Techniques
Intel 80310 I/O Processor Chipset AAU Coding Techniques
Intel 80310 I/O Processor Chipset AAU Coding Techniques
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<strong>Intel</strong> ® <strong>80310</strong> I/O <strong>Processor</strong> <strong>Chipset</strong> <strong>AAU</strong> <strong>Coding</strong> <strong>Techniques</strong>MMU Functions for <strong>Intel</strong> ® XScale Microarchitecture** The <strong>Intel</strong> ® XScale microarchitecture implements support for locking entries into* the data and instruction cache. The following functions implement the core* low level instructions needed to accomplish the locking. The developer's* manual states that the code that performs the locking must be in non-cached* memory. To accomplish this, the code in xscale-cache-lock.c copies the* following functions from the cache into a non-cached memory region that* is allocated through consistent_alloc().**/.align5/** xscale_icache_lock** r0: starting address to lock* r1: end address to lock*/ENTRY(xscale_icache_lock)iLockLoop:bic r0, r0, #CACHELINESIZE - 1mcr p15, 0, r0, c9, c1, 0@ lock into cachecmp r0, r1@ are we done?add r0, r0, #CACHELINESIZE@ advance to next cache linebls iLockLoopmov pc, lr/** xscale_icache_unlock*/ENTRY(xscale_icache_unlock)mcr p15, 0, r0, c9, c1, 1@ Unlock icachemov pc, lr86 White Paper
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