Intel 80310 I/O Processor Chipset AAU Coding Techniques
Intel 80310 I/O Processor Chipset AAU Coding Techniques
Intel 80310 I/O Processor Chipset AAU Coding Techniques
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<strong>Intel</strong> ® <strong>80310</strong> I/O <strong>Processor</strong> <strong>Chipset</strong> <strong>AAU</strong> <strong>Coding</strong> <strong>Techniques</strong>MMU Functions for <strong>Intel</strong> ® XScale Microarchitecturesubsr1, r1, #4 * CACHELINESIZEbne 1bmcr p15, 0, ip, c7, c10, 4@ Drain Write (& Fill) Buffermov pc, lr/** cpu_xscale_dcache_clean_entry(addr)** Clean the specified entry of any caches such that the MMU* translation fetches will obtain correct data.** addr: cache-unaligned virtual address*/.align5ENTRY(cpu_xscale_dcache_clean_entry)mcr p15, 0, r0, c7, c10, 1@ Clean D cache linemcr p15, 0, ip, c7, c10, 4@ Drain Write (& Fill) Buffermov pc, lr/* ================================ I-CACHE =============================== *//** cpu_xscale_icache_invalidate_range(start, end)** invalidate a range of virtual addresses from the Icache** start: virtual start address* end: virtual end address** Note: This is vaguely defined as supposed to bring the dcache and the* icache in sync by the way this function is used.*/.align5ENTRY(cpu_xscale_icache_invalidate_range)84 White Paper
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