Intel 80310 I/O Processor Chipset AAU Coding Techniques

Intel ® 80310 I/O Processor Chipset AAU Coding TechniquesCode Commentary4.1.2 Cache MemoryThe following function is required for AAU descriptors since cache memory and RAM coherenceare required to be managed by the programmer. Remember the AAU engine reads the AAUdescriptors from RAM. Therefore values in cache are required to be flushed by the programmer toRAM (see Appendix C in this document for implementation).• cpu_xscale_dcache_clean_range(start, end)For the specified virtual address range, ensure that all caches containclean data, such that peripheral accesses to the physical RAM fetchcorrect data.start: virtual start addressend: virtual end address4.1.3 Other AAU HardwareThe AAU hardware is described in the Intel ® 80312 I/O Companion Chip Developer’s Manualpages 10-1 through 10-33. For register definitions see pages 10-23 through 10-31.In the Appendix A code, see Descriptor Control Register (DC) bit definitions line 40 through line54. For Accelerator Control Register (ACR) and Accelerator Status Register (ASR) see bitdefinitions at lines 124 through 136.The addresses for referencing the memory mapped registers are references using #defines. Seeexamples in code lines 301, 305 and 320.• IOP310_AAUANDAR - Address of Accelerator next Descriptor Address Register• IOP310_AAUACR - Address of Accelerator Control Register• IOP310_AAUASR - Address of Accelerator Status Register4.1.4 Virtual to Physical memoryCache flush/invalidate and memory mapped registers operate with virtual memory addressesAAU descriptor operations operate from physical memory and require physical addresses. Forexample see Appendix A.3, line895.White Paper 27