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Intel 80310 I/O Processor Chipset AAU Coding Techniques

Intel 80310 I/O Processor Chipset AAU Coding Techniques

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<strong>Intel</strong> ® <strong>80310</strong> I/O <strong>Processor</strong> <strong>Chipset</strong> <strong>AAU</strong> <strong>Coding</strong> <strong>Techniques</strong>MMU Functions for <strong>Intel</strong> ® XScale Microarchitecture** Set a PTE and flush it out*/.align5ENTRY(cpu_xscale_set_pte)str r1, [r0], #-1024@ linux versionbic r2, r1, #0xff0bic r2, r2, #3eor r1, r1, #LPTE_PRESENT | LPTE_YOUNG | LPTE_WRITE | LPTE_DIRTY |LPTE_BUFFERABLE | LPTE_CACHEABLEtst r1, #LPTE_USER | LPTE_EXEC@ User or Exec?orrner2, r2, #HPTE_AP_READtst r1, #LPTE_WRITE | LPTE_DIRTY@ Write and Dirty?orreqr2, r2, #HPTE_AP_WRITE#if USER_CACHE_WRITE_ALLOCATEtst r1, #LPTE_CACHEABLE | LPTE_BUFFERABLE@ B and Corrner2, r2, #HPTE_TYPE_SMALLbiceqr2, r2, #0x0fc0@ clear non-exist AP[1-3]orreqr2, r2, #HPTE_TYPE_SMALLEXT | HPTE_SMALLEXT_TEX_X#elseorr r2, r2, #HPTE_TYPE_SMALL#endiftst r1, #LPTE_PRESENT | LPTE_YOUNG@ Present and Young?movner2, #0str r2, [r0]@ hardware versionmov r0, r0mcr p15, 0, r0, c7, c10, 1@ Clean D cache lineWhite Paper 93

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