Intel 80310 I/O Processor Chipset AAU Coding Techniques
Intel 80310 I/O Processor Chipset AAU Coding Techniques
Intel 80310 I/O Processor Chipset AAU Coding Techniques
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<strong>Intel</strong> ® <strong>80310</strong> I/O <strong>Processor</strong> <strong>Chipset</strong> <strong>AAU</strong> <strong>Coding</strong> <strong>Techniques</strong>MMU Functions for <strong>Intel</strong> ® XScale Microarchitecture*/.align5ENTRY(cpu_xscale_set_pgd)clean_d_cache r1, r2mcr p15, 0, ip, c7, c5, 0@ Invalidate I cache & BTBmcr p15, 0, ip, c7, c10, 4@ Drain Write (& Fill) Buffermcr p15, 0, r0, c2, c0, 0@ load page table pointermcr p15, 0, ip, c8, c7, 0@ invalidate I & D TLBscpwait_ret lr, ip/** cpu_xscale_set_pmd(pmdp, pmd)** Set a level 1 translation table entry, and clean it out of* any caches such that the MMUs can load it correctly.** pmdp: pointer to PMD entry* pmd: PMD value to store*/.align5ENTRY(cpu_xscale_set_pmd)#if KERN_CACHE_WRITE_ALLOCATEand r2, r1, #PMD_TYPE_MASK|PMD_SECT_CACHEABLE|PMD_SECT_BUFFERABLEcmp r2, #PMD_TYPE_SECT|PMD_SECT_CACHEABLE|PMD_SECT_BUFFERABLEorreqr1, r1, #PMD_SECT_TEX_X#endifstr r1, [r0]mcr p15, 0, r0, c7, c10, 1@ Clean D cache linemcr p15, 0, ip, c7, c10, 4@ Drain Write (& Fill) Buffermov pc, lr/** cpu_xscale_set_pte(ptep, pte)92 White Paper
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