Intel 80310 I/O Processor Chipset AAU Coding Techniques
Intel 80310 I/O Processor Chipset AAU Coding Techniques
Intel 80310 I/O Processor Chipset AAU Coding Techniques
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<strong>Intel</strong> ® <strong>80310</strong> I/O <strong>Processor</strong> <strong>Chipset</strong> <strong>AAU</strong> <strong>Coding</strong> <strong>Techniques</strong>MMU Functions for <strong>Intel</strong> ® XScale Microarchitecturemcr p15, 0, ip, c7, c10, 4@ Drain Write (& Fill) Buffermcr p15, 0, ip, c9, c2, 1@ Unlock cachemov pc, lr/** Needed to determine the length of the code that needs to be copied.*/.align5ENTRY(xscale_cache_dummy)mov pc, lr/* ================================== TLB ================================= *//** cpu_xscale_tlb_invalidate_all()** Invalidate all TLB entries*/.align5ENTRY(cpu_xscale_tlb_invalidate_all)mcr p15, 0, ip, c7, c10, 4@ Drain Write (& Fill) Buffermcr p15, 0, ip, c8, c7, 0@ invalidate I & D TLBscpwait_ret lr, ip/** cpu_xscale_tlb_invalidate_range(start, end)** invalidate TLB entries covering the specified range** start: range start address* end: range end address*/.align5ENTRY(cpu_xscale_tlb_invalidate_range)88 White Paper