NoC design and optimization for Multi-core media processors

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List of Tables3.1 ICN exploration framework parameters. . . . . . . . . . . . . . . . . . . . . 353.2 TrafficGeneration/DistributionModelandExperimentSetupfortheMesh,Torus & Folded-Torus case study. . . . . . . . . . . . . . . . . . . . . . . . 363.3 Links and pipelining details of NoCs . . . . . . . . . . . . . . . . . . . . . 403.4 DLA traffic, Frequency crossover points in 2D Mesh . . . . . . . . . . . . . 493.5 Comparison of 3 topologies for DLA traffic. . . . . . . . . . . . . . . . . . 493.6 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503.7 Links and pipelining details of NoCs . . . . . . . . . . . . . . . . . . . . . 513.8 Power optimal frequency trip points in a various NoCs. . . . . . . . . . . . 573.9 Comparison of 3 topologies. Maximum interconnect network performanceand power consumption for varying pipe stages. . . . . . . . . . . . . . . . 584.1 Configuration parameters of processors, caches & interconnection networkused in experiments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744.2 Scaled processor power over L1 configurations. . . . . . . . . . . . . . . . . 774.3 PrimaryandSecondarycacheparameters(accesstime, area)obtainedfromcacti. L2 access latencies as a function of L1 access times is also shown. . . 774.4 Max operating frequencies, Dynamic energy per access of various L1/L2caches. Values were calculated using cacti power models using 32nm PTM. 784.5 Lengths of links between L1/L2 caches & routers and between routers ofneighbouring tiles for a regular mesh placement. No. of pipeline stagesrequired to meet the maximum frequency are also shown. . . . . . . . . . . 794.6 FFT. Power spent in links (in mW). . . . . . . . . . . . . . . . . . . . . . 894.7 Total messages in transit (in Millions). . . . . . . . . . . . . . . . . . . . . 934.8 Clustered tile placement floorplan for L1: 256KB and L2: 512KB. Lengthsoflinks between neighbouringrouters, numberofpipelinestagesare shown.Frequency: 1.38 GHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975.1 Communication characteristics between HiperLAN/2 nodes. . . . . . . . . 1025.2 Routing table of a n port (n = 5) router with a lw bit (lw = 4) labelindexed by labels used in the label switched NoC. Size of the routing table= 2 lw ×n×lw. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095.3 Simulation parameters used for functional verification of the label switchedrouter design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113xi
LIST OF TABLESxii5.4 Synthesis Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135.5 Synthesis results 2 Router and Mesh networks. Area of a Router is 0.431mm 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146.1 NoC Manager Overhead. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227.1 Pipes set up for HiperLAN/2 baseband processing SoC and Object RecognitionProcessor SoC (Figure 7.1(a)). PEC[0-7]→PEC[0-7]: every PECcommunicates with every other PEC. . . . . . . . . . . . . . . . . . . . . . 1307.2 Standard test videos used in experiments. . . . . . . . . . . . . . . . . . . 1327.3 Evaluation of the proposed Label Switched Router and NoC. CS: Circuitswitched, PS: Packet switched. . . . . . . . . . . . . . . . . . . . . . . . . . 136A.1 ICN exploration framework parameters and their default values. . . . . . . 147C.1 Routing tables at R0 I0, R0 I2 and R1 I4 nodes after pipes P0 and P1 havebeen set up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Page 1 and 2: NoC Design & Optimization of Multic
Page 3 and 4: Abstractiibit data bus, 4 bit label
Page 5 and 6: Abstractivinterconnect latency.Simu
Page 7 and 8: PublicationsJournals• Basavaraj T
Page 9 and 10: CONTENTSviii2.4 Summary . . . . . .
Page 11: CONTENTSxC The Flow Algorithm 155C.
Page 15 and 16: LIST OF FIGURESxiv3.16 Schematic re
Page 17 and 18: LIST OF FIGURESxviB.3 8×8 mesh use
Page 19 and 20: CHAPTER 1. INTRODUCTION 2there is a
Page 21 and 22: CHAPTER 1. INTRODUCTION 4A few prop
Page 23 and 24: CHAPTER 1. INTRODUCTION 6Figure 1.1
Page 25 and 26: CHAPTER 1. INTRODUCTION 8link micro
Page 27 and 28: CHAPTER 1. INTRODUCTION 10identify
Page 29 and 30: CHAPTER 2. RELATED WORK 12this sect
Page 31 and 32: CHAPTER 2. RELATED WORK 14Æthereal
Page 33 and 34: CHAPTER 2. RELATED WORK 16in [64] a
Page 35 and 36: CHAPTER 2. RELATED WORK 18the overa
Page 37 and 38: CHAPTER 2. RELATED WORK 20Intacte[8
Page 39 and 40: CHAPTER 2. RELATED WORK 22predict t
Page 41 and 42: CHAPTER 2. RELATED WORK 24Sapphire[
Page 43 and 44: CHAPTER 2. RELATED WORK 26case, ban
Page 45 and 46: CHAPTER 2. RELATED WORK 28Level-2 c
Page 47 and 48: Chapter 3Link Microarchitecture Exp
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CHAPTER 3. LINK MICROARCHITECTURE E
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CHAPTER 4. TILE EXPLORATION 62inclu
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CHAPTER 4. TILE EXPLORATION 64Execu
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CHAPTER 4. TILE EXPLORATION 66reduc
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CHAPTER 4. TILE EXPLORATION 68laten
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CHAPTER 4. TILE EXPLORATION 70local
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CHAPTER 4. TILE EXPLORATION 72each
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CHAPTER 4. TILE EXPLORATION 74Table
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CHAPTER 4. TILE EXPLORATION 76of op
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CHAPTER 4. TILE EXPLORATION 78Table
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CHAPTER 4. TILE EXPLORATION 80FFT.
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CHAPTER 4. TILE EXPLORATION 82Progr
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CHAPTER 4. TILE EXPLORATION 84resul
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CHAPTER 4. TILE EXPLORATION 906560F
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CHAPTER 4. TILE EXPLORATION 92Progr
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CHAPTER 4. TILE EXPLORATION 964.9 I
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CHAPTER 4. TILE EXPLORATION 981.151
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Chapter 5Label Switched NoC - Motiv
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CHAPTER 5. LABEL SWITCHED NOC 102Ta
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CHAPTER 5. LABEL SWITCHED NOC 104co
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CHAPTER 5. LABEL SWITCHED NOC 1065.
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CHAPTER 5. LABEL SWITCHED NOC 108
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CHAPTER 5. LABEL SWITCHED NOC 110IN
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CHAPTER 5. LABEL SWITCHED NOC 1120R
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Chapter 6LS-NoC ManagementStreaming
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CHAPTER 6. LS-NOC MANAGEMENT 118abi
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CHAPTER 6. LS-NOC MANAGEMENT 120the
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CHAPTER 6. LS-NOC MANAGEMENT 122Tab
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CHAPTER 6. LS-NOC MANAGEMENT 124Vid
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CHAPTER 6. LS-NOC MANAGEMENT 126S0l
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CHAPTER 6. LS-NOC MANAGEMENT 128Flo
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CHAPTER 7. LABEL SWITCHED NOC 132OR
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CHAPTER 7. LABEL SWITCHED NOC 1347.
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CHAPTER 7. LABEL SWITCHED NOC 136LS
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CHAPTER 7. LABEL SWITCHED NOC 138co
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Chapter 8Conclusion and Future Work
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CHAPTER 8. CONCLUSION AND FUTURE WO
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CHAPTER 8. CONCLUSION AND FUTURE WO
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Appendix AInterface and Outputs of
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APPENDIXA. INTERFACEANDOUTPUTSOFTHE
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Appendix BTesting & Validation of L
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APPENDIX B. TESTING & VALIDATION OF
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APPENDIX B. TESTING & VALIDATION OF
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APPENDIX C. THE FLOW ALGORITHM 156X
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APPENDIX C. THE FLOW ALGORITHM 158E
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Bibliography[1] W.J. Dally and B. T
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BIBLIOGRAPHY 162[16] C. Hilton and
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BIBLIOGRAPHY 164[32] ErnoSalminen,T
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BIBLIOGRAPHY 166[50] Erno Salminen,
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BIBLIOGRAPHY 168[66] N. Megiddo. Op
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BIBLIOGRAPHY 170[84] B.S. Landman a
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BIBLIOGRAPHY 172[101] Michael Huang
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BIBLIOGRAPHY 174[118] J Gonzlez and
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BIBLIOGRAPHY 176[133] Ron Ho, Kenne
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NoC design and optimization for Multi-core media processors

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