NoC design and optimization for Multi-core media processors

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List of Figures1.1 Design space exploration of NoCs in CMPs are closely related to link microarchitecture,router design and tile configurations. . . . . . . . . . . . . 62.1 Floorplan used in estimating wire lengths. Wire lengths estimated fromthese floorplans are used as input to Intacte to arrive at a power optimalconfiguration and latency in clock cycles. Horizontal R-R: Link betweenneighboring routers in the horizontal direction, Vertical R-R: Link betweenneighbouring routers in the vertical direction. . . . . . . . . . . . . . . . . 253.1 Architecture of the SystemC framework. . . . . . . . . . . . . . . . . . . . 343.2 Flow of the ICN exploration framework. . . . . . . . . . . . . . . . . . . . 343.3 Flit header format. DSTID/SRCID: Destination/Source ID, SQ:SequenceNumber, RQ & RP: Request and Response Flags and a 13 bit flit id. . . . 363.4 Example flit header formats considered in this experiment. (DST/SRCID:Destination/Source ID, HC:Hop Count, CHNx:Direction at hop x). . . . . 373.5 Schematic of 3 compared topologies (L to R: Mesh, Torus, Folded Torus).Routers are shaded and Processing Elements(PE) are not. . . . . . . . . . 393.6 Normalized average round trip latency in cycles vs. Traffic injection ratein all the 3 NoCs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413.7 Max. frequency of links in 3 topologies. Lengths of longest links in Mesh,Torus and Folded 2D Torus are 2.5mm, 8.15mm and 5.5mm. . . . . . . . . 423.8 Total NoC throughput in 3 topologies, DLA traffic. . . . . . . . . . . . . . 433.9 Avg. round trip flit latency in 3 NoCs, DLA traffic. . . . . . . . . . . . . . 433.10 2D Mesh Power/Throughput/Latency trade-offs for DLA traffic. Normalizedresults are shown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443.11 2D Mesh Power/Throughput/Latency trade-offs for SLA traffic. . . . . . . 443.12 DLATraffic, 2DTorusPower/Throughput/Latencytrade-offs. Normalizedresults are shown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453.13 DLATraffic,Folded2DTorusPower/Throughput/Latencytrade-offs. Normalizedresults are shown. . . . . . . . . . . . . . . . . . . . . . . . . . . . 463.14 Frequency scaling on 3 topologies, DLA Traffic. . . . . . . . . . . . . . . . 473.15 Dynamic voltage scaling on 2D Mesh, DLA Traffic. Frequency scaled curvefor P=8 is also shown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48xiii
LIST OF FIGURESxiv3.16 Schematic representation of the three compared topologies (L to R: 2DTorus, Tree, Reduced 2D Torus). Shaded rectangles are Routers and whiteboxes are source/sink Processing Elements(PE) nodes. . . . . . . . . . . . 503.17 Floorplans of the three compared topologies. . . . . . . . . . . . . . . . . . 513.18 Maximum attainable frequency by links in the respective topologies. Estimatedlength of the longest link in a 2D Torus is 7mm. Estimated longestlink in the Tree based and Reduced 2D Torus is 3.5mm. . . . . . . . . . . . 523.19 Variation of total NoC throughput with varying pipeline stages in all threetopologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533.20 2D Torus Power/Throughput/Latency trade-offs. Normalized results areshown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543.21 Reduced 2D Torus Power/Throughput/Latency trade-offs. Normalized resultsare shown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553.22 Variation of NoC power with throughput for each topology. . . . . . . . . . 563.23 Effects of dynamic voltage scaling on the power and performance of a 2DTorus. Highest frequency of operation for P=1, 2, 4 and 7 are .93GHz,1.68GHz, 2.92GHz and 4.22GHz. Power consumption of the frequencyscaled NoC is shown for comparison. . . . . . . . . . . . . . . . . . . . . . 574.1 Error in performance measurement between real and ideal interconnectexperiments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644.2 Schematic of a multiprocessor architecture comprising of tiles and an interconnectingnetwork. Each tile is made up of a processor, L1 and L2caches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674.3 Flowchart illustrating the steps in experimental procedure. . . . . . . . . . 754.4 Tile floorplans for different(L1, L2) sizes. Fromleft: (8KB, 64KB), (64KB,1MB), (128KB, 4MB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774.5 Mesh floorplans used in experiments. From left: Conventional 2D Meshtopology, a clustered topology, cluster topology with L2 bank and threadmapping and and a mesh topology with L2 bank and thread mapping. . . . 774.6 Benchmark execution time vs. Communication time - DRAM access timeand On-chip transit time vs. L2 cache size vs. Program completion time. . 804.7 Program energy vs. Communication time. . . . . . . . . . . . . . . . . . . 814.8 64K point FFT benchmark execution time vs. Total time spent in on-chipmessage transit. L2 cache sizes are in the order 64KB, 128KB, 256KB,512KB, 1M, 2M, 4M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824.9 64K point FFT execution time vs. Total time spent in DRAM (off-chip)accesses. L2 cache sizes are in the order 64KB, 128KB, 256KB, 512KB,1M, 2M, 4M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854.10 Total messages over all the links during the execution of the benchmarkand Average transit time of a message. . . . . . . . . . . . . . . . . . . . . 864.11 FFT. Totalinstructionsexecutedand power spentin thememoryhierarchyand on-chip links during the execution. . . . . . . . . . . . . . . . . . . . . 88
Page 1 and 2: NoC Design & Optimization of Multic
Page 3 and 4: Abstractiibit data bus, 4 bit label
Page 5 and 6: Abstractivinterconnect latency.Simu
Page 7 and 8: PublicationsJournals• Basavaraj T
Page 9 and 10: CONTENTSviii2.4 Summary . . . . . .
Page 11 and 12: CONTENTSxC The Flow Algorithm 155C.
Page 13: LIST OF TABLESxii5.4 Synthesis Para
Page 17 and 18: LIST OF FIGURESxviB.3 8×8 mesh use
Page 19 and 20: CHAPTER 1. INTRODUCTION 2there is a
Page 21 and 22: CHAPTER 1. INTRODUCTION 4A few prop
Page 23 and 24: CHAPTER 1. INTRODUCTION 6Figure 1.1
Page 25 and 26: CHAPTER 1. INTRODUCTION 8link micro
Page 27 and 28: CHAPTER 1. INTRODUCTION 10identify
Page 29 and 30: CHAPTER 2. RELATED WORK 12this sect
Page 31 and 32: CHAPTER 2. RELATED WORK 14Æthereal
Page 33 and 34: CHAPTER 2. RELATED WORK 16in [64] a
Page 35 and 36: CHAPTER 2. RELATED WORK 18the overa
Page 37 and 38: CHAPTER 2. RELATED WORK 20Intacte[8
Page 39 and 40: CHAPTER 2. RELATED WORK 22predict t
Page 41 and 42: CHAPTER 2. RELATED WORK 24Sapphire[
Page 43 and 44: CHAPTER 2. RELATED WORK 26case, ban
Page 45 and 46: CHAPTER 2. RELATED WORK 28Level-2 c
Page 47 and 48: Chapter 3Link Microarchitecture Exp
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CHAPTER 3. LINK MICROARCHITECTURE E
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CHAPTER 4. TILE EXPLORATION 62inclu
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CHAPTER 4. TILE EXPLORATION 64Execu
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CHAPTER 4. TILE EXPLORATION 66reduc
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CHAPTER 4. TILE EXPLORATION 68laten
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CHAPTER 4. TILE EXPLORATION 70local
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CHAPTER 4. TILE EXPLORATION 72each
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CHAPTER 4. TILE EXPLORATION 74Table
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CHAPTER 4. TILE EXPLORATION 78Table
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CHAPTER 4. TILE EXPLORATION 80FFT.
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CHAPTER 4. TILE EXPLORATION 82Progr
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CHAPTER 4. TILE EXPLORATION 906560F
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CHAPTER 4. TILE EXPLORATION 92Progr
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CHAPTER 4. TILE EXPLORATION 964.9 I
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CHAPTER 4. TILE EXPLORATION 981.151
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Chapter 5Label Switched NoC - Motiv
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Chapter 6LS-NoC ManagementStreaming
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CHAPTER 6. LS-NOC MANAGEMENT 118abi
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CHAPTER 6. LS-NOC MANAGEMENT 120the
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CHAPTER 6. LS-NOC MANAGEMENT 122Tab
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CHAPTER 6. LS-NOC MANAGEMENT 124Vid
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CHAPTER 6. LS-NOC MANAGEMENT 126S0l
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CHAPTER 6. LS-NOC MANAGEMENT 128Flo
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Chapter 8Conclusion and Future Work
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CHAPTER 8. CONCLUSION AND FUTURE WO
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CHAPTER 8. CONCLUSION AND FUTURE WO
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Appendix AInterface and Outputs of
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APPENDIXA. INTERFACEANDOUTPUTSOFTHE
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Appendix BTesting & Validation of L
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APPENDIX B. TESTING & VALIDATION OF
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APPENDIX B. TESTING & VALIDATION OF
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APPENDIX C. THE FLOW ALGORITHM 156X
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APPENDIX C. THE FLOW ALGORITHM 158E
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Bibliography[1] W.J. Dally and B. T
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BIBLIOGRAPHY 162[16] C. Hilton and
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BIBLIOGRAPHY 164[32] ErnoSalminen,T
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BIBLIOGRAPHY 166[50] Erno Salminen,
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BIBLIOGRAPHY 168[66] N. Megiddo. Op
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BIBLIOGRAPHY 170[84] B.S. Landman a
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BIBLIOGRAPHY 172[101] Michael Huang
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BIBLIOGRAPHY 174[118] J Gonzlez and
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BIBLIOGRAPHY 176[133] Ron Ho, Kenne
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NoC design and optimization for Multi-core media processors

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