NoC design and optimization for Multi-core media processors

More documents

Recommendations

Info

Chapter 2Related WorkSeveralpublicationshavehighlightedtheneedforsolutionstopressingproblemsinvariousdomains in the broad area of Network-on-Chips[47][48][49][50]. This chapter introducesrelevant works in the broad areas of QoS guaranteed Network-on-Chips, design spaceexploration of NoCs and effects of communication on energy and performance trade-offsin CMPs.2.1 Traffic Engineered NoC for Streaming ApplicationsProviding QoS guarantees in on-chip communication networks has been identified as oneof major research problems in NoCs[48]. QoS solutions in packet switched networks usepriority based services while circuit switched NoCs use some form of resource reservation.We introduce a few well known QoS solutions from literature and compare our work withthe state of the art. Packet switched NoCs use differentiated services for traffic classes[29][22][21][8] to provide latency and bandwidth guarantees. Circuit switched NoCs useresource reservation mechanisms to guarantee QoS[34][51][41][19]. Resource reservationmechanisms involve identifying a sufficiently resource rich path, reserving resources alongthe path, configuration, actual communication and path tear down. A fairly extensivesurvey of NoC proposals has been presented in [50]. Relevant QoS NoCs are discussed in11
CHAPTER 2. RELATED WORK 12this section.2.1.1 QoS in Packet Switched NetworksQoS NoC (QNoC) presented by Bolotin et. al. [29] is a customized QoS NoC architecturebasedona2DMeshtosatisfyQoSbyallocatingfrequentlycommunicatingnodesclose-by,doing away with unnecessary links, tailoring link width to meet bandwidth requirementsand balancing link utilization. Inter-module communication traffic is classified into fourclasses of service: signaling, real-time, RD/WR and block-transfer. FAUST[22] is a reconfigurablebaseband platform based on an asynchronous NoC providing a programmablecommunication framework linking heterogeneous resources. FAUST uses 2 level prioritybasedvirtualcircuitdesigninitsNetworkInterface(NI)toprovideQoSguarantees. AsynchronousNoCs[21] use clock-free interconnect to improve reliability and delay-insensitivearbiters to solve routing conflicts. A QoS Router with both soft (Soft GT) and hard (HardGT) guarantees for globally asynchronous, locally synchronous (GALS) NoCs is presentedin [52]. Leftover bandwidth in routers servicing Hard GT is utilized by Soft GT connectionsand best effort traffic. NoCs presented in [21], [52] and [53] employ multiple prioritylevels to provide differentiated services and guarantee QoS. The MANGO [27][54] NoCprovides hard GT by prioritizing each GT connection and adopts Asynchronous LatencyGuarantee (ALG) scheduling to prevent starvation of packets with lower priority.One of the major drawbacks of priority based QoS schemes is that increase in trafficin one priority class effects the delay on traffic belonging to other classes. A prioritynetwork will lose the differentiated services advantage if all traffic belong to the samepriority level. Further, deadlock-free routing algorithms using virtual circuits with apriorityapproachmayleadtodegradationinNoCthroughput. Incaseswhereconnectionscannot be overlapped with each other (eg. MANGO NoC), increased number of hard GTconnections will lead to increased cost in network resources.Another class of packet switched NoCs using priority based QoS solutions are applicationspecific SoCs. A tree based hierarchical packet-switched NoC for a real-time objectrecognition processor is implemented in [8]. The tree topology NoC with three crossbar
Page 1 and 2: NoC Design & Optimization of Multic
Page 3 and 4: Abstractiibit data bus, 4 bit label
Page 5 and 6: Abstractivinterconnect latency.Simu
Page 7 and 8: PublicationsJournals• Basavaraj T
Page 9 and 10: CONTENTSviii2.4 Summary . . . . . .
Page 11 and 12: CONTENTSxC The Flow Algorithm 155C.
Page 13 and 14: LIST OF TABLESxii5.4 Synthesis Para
Page 15 and 16: LIST OF FIGURESxiv3.16 Schematic re
Page 17 and 18: LIST OF FIGURESxviB.3 8×8 mesh use
Page 19 and 20: CHAPTER 1. INTRODUCTION 2there is a
Page 21 and 22: CHAPTER 1. INTRODUCTION 4A few prop
Page 23 and 24: CHAPTER 1. INTRODUCTION 6Figure 1.1
Page 25 and 26: CHAPTER 1. INTRODUCTION 8link micro
Page 27: CHAPTER 1. INTRODUCTION 10identify
Page 31 and 32: CHAPTER 2. RELATED WORK 14Æthereal
Page 33 and 34: CHAPTER 2. RELATED WORK 16in [64] a
Page 35 and 36: CHAPTER 2. RELATED WORK 18the overa
Page 37 and 38: CHAPTER 2. RELATED WORK 20Intacte[8
Page 39 and 40: CHAPTER 2. RELATED WORK 22predict t
Page 41 and 42: CHAPTER 2. RELATED WORK 24Sapphire[
Page 43 and 44: CHAPTER 2. RELATED WORK 26case, ban
Page 45 and 46: CHAPTER 2. RELATED WORK 28Level-2 c
Page 47 and 48: Chapter 3Link Microarchitecture Exp
Page 49 and 50: CHAPTER 3. LINK MICROARCHITECTURE E
Page 79 and 80:
CHAPTER 4. TILE EXPLORATION 62inclu
Page 81 and 82:
CHAPTER 4. TILE EXPLORATION 64Execu
Page 83 and 84:
CHAPTER 4. TILE EXPLORATION 66reduc
Page 85 and 86:
CHAPTER 4. TILE EXPLORATION 68laten
Page 87 and 88:
CHAPTER 4. TILE EXPLORATION 70local
Page 89 and 90:
CHAPTER 4. TILE EXPLORATION 72each
Page 91 and 92:
CHAPTER 4. TILE EXPLORATION 74Table
Page 93 and 94:
CHAPTER 4. TILE EXPLORATION 76of op
Page 95 and 96:
CHAPTER 4. TILE EXPLORATION 78Table
Page 97 and 98:
CHAPTER 4. TILE EXPLORATION 80FFT.
Page 99 and 100:
CHAPTER 4. TILE EXPLORATION 82Progr
Page 101 and 102:
CHAPTER 4. TILE EXPLORATION 84resul
Page 103 and 104:
Page 105 and 106:
Page 107 and 108:
CHAPTER 4. TILE EXPLORATION 906560F
Page 109 and 110:
CHAPTER 4. TILE EXPLORATION 92Progr
Page 111 and 112:
Page 113 and 114:
CHAPTER 4. TILE EXPLORATION 964.9 I
Page 115 and 116:
CHAPTER 4. TILE EXPLORATION 981.151
Page 117 and 118:
Chapter 5Label Switched NoC - Motiv
Page 119 and 120:
CHAPTER 5. LABEL SWITCHED NOC 102Ta
Page 121 and 122:
CHAPTER 5. LABEL SWITCHED NOC 104co
Page 123 and 124:
CHAPTER 5. LABEL SWITCHED NOC 1065.
Page 125 and 126:
CHAPTER 5. LABEL SWITCHED NOC 108
Page 127 and 128:
CHAPTER 5. LABEL SWITCHED NOC 110IN
Page 129 and 130:
CHAPTER 5. LABEL SWITCHED NOC 1120R
Page 131 and 132:
Page 133 and 134:
Chapter 6LS-NoC ManagementStreaming
Page 135 and 136:
CHAPTER 6. LS-NOC MANAGEMENT 118abi
Page 137 and 138:
CHAPTER 6. LS-NOC MANAGEMENT 120the
Page 139 and 140:
CHAPTER 6. LS-NOC MANAGEMENT 122Tab
Page 141 and 142:
CHAPTER 6. LS-NOC MANAGEMENT 124Vid
Page 143 and 144:
CHAPTER 6. LS-NOC MANAGEMENT 126S0l
Page 145 and 146:
CHAPTER 6. LS-NOC MANAGEMENT 128Flo
Page 147 and 148:
Page 149 and 150:
CHAPTER 7. LABEL SWITCHED NOC 132OR
Page 151 and 152:
CHAPTER 7. LABEL SWITCHED NOC 1347.
Page 153 and 154:
CHAPTER 7. LABEL SWITCHED NOC 136LS
Page 155 and 156:
CHAPTER 7. LABEL SWITCHED NOC 138co
Page 157 and 158:
Chapter 8Conclusion and Future Work
Page 159 and 160:
CHAPTER 8. CONCLUSION AND FUTURE WO
Page 161 and 162:
CHAPTER 8. CONCLUSION AND FUTURE WO
Page 163 and 164:
Appendix AInterface and Outputs of
Page 165 and 166:
APPENDIXA. INTERFACEANDOUTPUTSOFTHE
Page 167 and 168:
Appendix BTesting & Validation of L
Page 169 and 170:
APPENDIX B. TESTING & VALIDATION OF
Page 171 and 172:
APPENDIX B. TESTING & VALIDATION OF
Page 173 and 174:
APPENDIX C. THE FLOW ALGORITHM 156X
Page 175 and 176:
APPENDIX C. THE FLOW ALGORITHM 158E
Page 177 and 178:
Bibliography[1] W.J. Dally and B. T
Page 179 and 180:
BIBLIOGRAPHY 162[16] C. Hilton and
Page 181 and 182:
BIBLIOGRAPHY 164[32] ErnoSalminen,T
Page 183 and 184:
BIBLIOGRAPHY 166[50] Erno Salminen,
Page 185 and 186:
BIBLIOGRAPHY 168[66] N. Megiddo. Op
Page 187 and 188:
BIBLIOGRAPHY 170[84] B.S. Landman a
Page 189 and 190:
BIBLIOGRAPHY 172[101] Michael Huang
Page 191 and 192:
BIBLIOGRAPHY 174[118] J Gonzlez and
Page 193 and 194:
BIBLIOGRAPHY 176[133] Ron Ho, Kenne
show all

NoC design and optimization for Multi-core media processors

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?