NoC design and optimization for Multi-core media processors

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CHAPTER 2. RELATED WORK 29product (of the NoC) as the optimization parameter.Communication effects need to be accounted into simulations as communication timeshave significant impact on performance and energy of CMPs. The trade-off between tilesize, communication time and energy efficiency has been explored in Chapter 4. We explorethese trade-offs using a detailed, cycle accurate, multicore simulation frameworkwhich includes superscalar processor cores, cache coherent memory hierarchies, on-chippointtopointcommunicationnetworksanddetailedinterconnectmodelincludingpipeliningand latency. CACTI[122] cache models are used to estimate area, energy per accessand leakage power of L1 & L2 caches and values from the SPARC processor[123] are usedfor processor power estimates.
Chapter 3Link Microarchitecture ExplorationThis chapter presents a latency, power and performance trade-offs of microarchitecturalparameters of NoCs. The design and implementation of a framework for such a designspace exploration study is also presented. The chapter presents the trade-off study onNoCs by varying microarchitectural (e.g. pipelining) and circuit level (e.g. frequencyand voltage) parameters. Though the study is done in the context of packet based NoC,the results are applicable to all NoCs as the parameters considered are low level linkparameters which are common to all NoCs.A System-C based NoC exploration framework presented here is used to explore impactsof various architectural and microarchitectural level parameters of NoC elements onpower and performance of the NoC. The framework enables the designer to choose from avariety of architectural options like topology, routing policy, etc., as well as allows experimentationwith various microarchitectural options for the individual links like length, wirewidth, pitch, pipelining, supply voltage and frequency. Network-on-Chip design parameterssuch as topology generation and link pipelining have varying impacts on throughputofthenetwork, latencyofflitsandpowerdissipationoftheNoCinanSoC.Theframeworkuses Intacte[82] to estimate delay and power based on micro-architecture parameters suchas wire length, wire width, activity for a given technology and voltage. The frameworkalso supports a flexible traffic generation and communication model. Latency, power andthroughput results using this framework to study a 4x4 CMP are presented. The chapter30
Page 1 and 2: NoC Design & Optimization of Multic
Page 3 and 4: Abstractiibit data bus, 4 bit label
Page 5 and 6: Abstractivinterconnect latency.Simu
Page 7 and 8: PublicationsJournals• Basavaraj T
Page 9 and 10: CONTENTSviii2.4 Summary . . . . . .
Page 11 and 12: CONTENTSxC The Flow Algorithm 155C.
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CHAPTER 4. TILE EXPLORATION 82Progr
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CHAPTER 4. TILE EXPLORATION 981.151
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Chapter 5Label Switched NoC - Motiv
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Chapter 6LS-NoC ManagementStreaming
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CHAPTER 6. LS-NOC MANAGEMENT 118abi
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CHAPTER 6. LS-NOC MANAGEMENT 120the
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CHAPTER 6. LS-NOC MANAGEMENT 122Tab
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CHAPTER 6. LS-NOC MANAGEMENT 124Vid
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CHAPTER 6. LS-NOC MANAGEMENT 126S0l
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CHAPTER 6. LS-NOC MANAGEMENT 128Flo
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Chapter 8Conclusion and Future Work
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CHAPTER 8. CONCLUSION AND FUTURE WO
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CHAPTER 8. CONCLUSION AND FUTURE WO
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Appendix AInterface and Outputs of
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APPENDIXA. INTERFACEANDOUTPUTSOFTHE
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Appendix BTesting & Validation of L
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APPENDIX B. TESTING & VALIDATION OF
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APPENDIX B. TESTING & VALIDATION OF
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APPENDIX C. THE FLOW ALGORITHM 156X
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APPENDIX C. THE FLOW ALGORITHM 158E
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Bibliography[1] W.J. Dally and B. T
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BIBLIOGRAPHY 162[16] C. Hilton and
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BIBLIOGRAPHY 164[32] ErnoSalminen,T
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BIBLIOGRAPHY 166[50] Erno Salminen,
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BIBLIOGRAPHY 168[66] N. Megiddo. Op
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BIBLIOGRAPHY 170[84] B.S. Landman a
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BIBLIOGRAPHY 172[101] Michael Huang
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BIBLIOGRAPHY 174[118] J Gonzlez and
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BIBLIOGRAPHY 176[133] Ron Ho, Kenne
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NoC design and optimization for Multi-core media processors

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