NoC design and optimization for Multi-core media processors

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CHAPTER 2. RELATED WORK 19router elements (crossbars, FIFOs and arbiters) by calculating switching capacitances ofindividual circuit elements. Orion contains a library of architectural level parameterizedpower models.The more recent Orion 2.0 presented in [76] is an enhanced NoC power and areasimulator offering improved accuracy compared to the original Orion framework. Some oftheadditionsintoOrion2.0includeflip-flopandclockdynamicandleakagepowermodels,link power models, leveraging models developed in [74]. Virtual Channel (VC) allocatormicroarchitectureusesaVCallocationmodel, basedonthemicroarchitectureandpipelineproposed in [77]. Application-specific technology-level fine tuning of parameters usingdifferent V th and transistor widths are used to increase accuracy of power estimation.Work in [72] explores use of heterogeneous interconnects optimized for delay, bandwidthorpowerbyvaryingdesignparameterssuchasabuffersizes,wirewidthandnumberof repeaters on the interconnects. The work presented in the paper uses Energy-Delay 2as the optimization parameter. An evaluation of different configurations of heterogeneousinterconnects is made. The evaluation shows that an optimal configuration (for delay,bandwidth, power or power and bandwidth) of wires can reduce the total processor ED 2value by up to 11% compared to a NoC with homogeneous interconnect in a typicalprocessor.Courtay et. al[73] have developed a high-level delay and power estimation tool forlink exploration that offers similar statistics as Intacte does. The tool allows changingarchitectural level parameters such as different signal coding techniques to analyze theeffects on wire delay/power.Work in [74] proposes delay and power models for buffered interconnects. The modelscan be constructed from sources such as Liberty[78], LEF/ITF[79], ITRS[80], andPTM[81]. The buffered delay models take into account effects of input and output slewsof circuit elements in calculating intrinsic delays. The power models include leakage anddynamic power dissipation of gates. The area models include technology dependent coefficientsthat can be estimated by linear regression techniques per technology node toestimate repeater areas.
CHAPTER 2. RELATED WORK 20Intacte[82] is used for interconnect delay and power estimates. Design variables forIntacte’sinterconnectoptimizationarewirewidth,wirespacing,repeatersizeandspacing,degreeofpipelining, supply(V dd )andthresholdvoltage(V th ). Intactecanbeusedtoarriveat power optimal number of repeaters, sizes and spacing for a given wire length to achievea desired frequency. Intacte outputs total power dissipated including short circuit andleakage power values.A high level power estimation tool accounting for interconnect effects is presented in[83]. The work presents an interconnect length estimation model based on Rent’s rule[84]and a high level area (gate count) prediction method. Different place and route enginesand cell libraries can be used with this proposed model after some minor adaptations.2.3.2 Router Power and Architecture Exploration ToolsMostrouterexplorationtoolsmodelICNelementsatahigherlevelabstractionofswitches,links and buffers and help in power/performance trade-off studies[85][86]. These are usedto research the design of router architectures[87] and ICN topologies[34] with varyingarea/performance trade-offs for general purpose SoCs or to cater to specific applications.A high level power estimation methodology for NoC routers based on number oftraversing flits as the unit of abstraction has been proposed in [85]. The macro model oftheframeworkincursaminorabsolutecycleerrorcomparedtogatelevelanalysis. Providinga fast and cycle accurate power profile at an early stage of router design enables poweroptimizations such as power-aware compilers, core mapping, and scheduling techniquesfor CMPs to be incorporated into the final design. The power macro model uses stateinformation of FSM in a router assigned to reserve channels during packet forwardingfor wormhole flow control. This enhances the accuracy of the power macro model. Thepower macro model based on regression analysis can be migrated to different technologylibraries.An architectural-level power model for interconnection network routers has been presentedin [88]. The work specifically considers the Alpha 21364 and Infiniband routers
Page 1 and 2: NoC Design & Optimization of Multic
Page 3 and 4: Abstractiibit data bus, 4 bit label
Page 5 and 6: Abstractivinterconnect latency.Simu
Page 7 and 8: PublicationsJournals• Basavaraj T
Page 9 and 10: CONTENTSviii2.4 Summary . . . . . .
Page 11 and 12: CONTENTSxC The Flow Algorithm 155C.
Page 13 and 14: LIST OF TABLESxii5.4 Synthesis Para
Page 15 and 16: LIST OF FIGURESxiv3.16 Schematic re
Page 17 and 18: LIST OF FIGURESxviB.3 8×8 mesh use
Page 19 and 20: CHAPTER 1. INTRODUCTION 2there is a
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Page 23 and 24: CHAPTER 1. INTRODUCTION 6Figure 1.1
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Page 33 and 34: CHAPTER 2. RELATED WORK 16in [64] a
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CHAPTER 4. TILE EXPLORATION 70local
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CHAPTER 4. TILE EXPLORATION 74Table
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CHAPTER 4. TILE EXPLORATION 76of op
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CHAPTER 4. TILE EXPLORATION 78Table
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CHAPTER 4. TILE EXPLORATION 80FFT.
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CHAPTER 4. TILE EXPLORATION 82Progr
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CHAPTER 4. TILE EXPLORATION 906560F
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CHAPTER 4. TILE EXPLORATION 92Progr
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CHAPTER 4. TILE EXPLORATION 964.9 I
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CHAPTER 4. TILE EXPLORATION 981.151
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Chapter 5Label Switched NoC - Motiv
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CHAPTER 5. LABEL SWITCHED NOC 102Ta
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Chapter 6LS-NoC ManagementStreaming
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CHAPTER 6. LS-NOC MANAGEMENT 118abi
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CHAPTER 6. LS-NOC MANAGEMENT 120the
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CHAPTER 6. LS-NOC MANAGEMENT 122Tab
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CHAPTER 6. LS-NOC MANAGEMENT 124Vid
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CHAPTER 6. LS-NOC MANAGEMENT 126S0l
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CHAPTER 6. LS-NOC MANAGEMENT 128Flo
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Chapter 8Conclusion and Future Work
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CHAPTER 8. CONCLUSION AND FUTURE WO
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CHAPTER 8. CONCLUSION AND FUTURE WO
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Appendix AInterface and Outputs of
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APPENDIXA. INTERFACEANDOUTPUTSOFTHE
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Appendix BTesting & Validation of L
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APPENDIX B. TESTING & VALIDATION OF
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APPENDIX B. TESTING & VALIDATION OF
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APPENDIX C. THE FLOW ALGORITHM 156X
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APPENDIX C. THE FLOW ALGORITHM 158E
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Bibliography[1] W.J. Dally and B. T
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BIBLIOGRAPHY 162[16] C. Hilton and
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BIBLIOGRAPHY 164[32] ErnoSalminen,T
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BIBLIOGRAPHY 166[50] Erno Salminen,
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BIBLIOGRAPHY 168[66] N. Megiddo. Op
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BIBLIOGRAPHY 170[84] B.S. Landman a
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BIBLIOGRAPHY 172[101] Michael Huang
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BIBLIOGRAPHY 174[118] J Gonzlez and
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BIBLIOGRAPHY 176[133] Ron Ho, Kenne
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NoC design and optimization for Multi-core media processors

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