NoC design and optimization for Multi-core media processors

CHAPTER 2. RELATED WORK 23framework quantifies power consumption of all the major units of the processor, parameterizethem, and integrate these power estimates into a high-level simulator. Wattchmodels main processor units into array structures, fully associative content-addressablememories,combinational logic and wires or clocking elements. Individual capacitancesof each of these elements are estimated and power is calculated. Work presented in [95]integrates Wattch into SimpleScalar architectural simulator[96].A tool like Ruby[97], allows one to simulate a complete distributed memory hierarchywith an on-chip network as in Orion. However, it needs to be augmented with a detailedinterconnect model which accounts for the physical area of the tiles and their placements.Network Processor exploration and power estimation tools utilize models for smallercomponents and quote the integrated power for the system[98][99][100]. They use cycleaccurate register, cache and arbiter models introduced previously here. NePSim[99] isan open-source integrated simulation infrastructure. Typical network processors can besimulated with the cycle accurate simulator inclusive in the framework. Testing andvalidation of results can be performed by an automatic verification framework. NePSimcombines various power models from Xcacti[101], Wattch[95] and Orion[71] for differenthardware structures in NePSim. XCacti[101] is an enhanced version of Cacti 2.0 thatincludes power modeling for cache writes, misses, and writebacks. NePSim classifies thenetwork processor components into categories such as ALU and shifter, registers, caches,queues and arbiters. The processor’s power consumption can be calculated using a powerand an estimation tool inbuilt into the framework.SapphireThe tile area optimization problem is closely knit with interconnect, cache and processorarchitecture exploration. There is a need for a co-design of interconnects, processingelements and memory blocks to fully optimize the overall multi-core chip performance.This necessitates a simulation framework which allows a co-simulation of processor cores,a detailed cache memory hierarchy, on-chip network, along with a low-level interconnectmodel.