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NoC design and optimization for Multi-core media processors

NoC design and optimization for Multi-core media processors

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CHAPTER 3. LINK MICROARCHITECTURE EXPLORATION 31presents results on power-per<strong>for</strong>mance trade-off studies on Mesh, Torus, Folded Torus,Tree based network <strong>and</strong> a Reduced 2D Torus topologies by varying pipelining in links <strong>and</strong>frequency <strong>and</strong> voltage scaling.The framework is used to study <strong>NoC</strong> <strong>design</strong>s of a CMP using different classes ofparallel computing benchmarks[6]. Traffic patterns from dense <strong>and</strong> sparse linear algebraapplicationsareusedinthisstudy. ThetrafficconsistsofbothRequest-Responsemessages(mimicking cache accesses) <strong>and</strong> One-Way messages. One of the key findings is that theaverage latency of a link can be reduced by increasing pipeline depth to a certain extent,as it enables link operation at higher link frequencies. There exists an optimum degree ofpipelining which minimizes the energy-delay product of the link.Using frequency scaling experiments we show that switching to a higher degree of linkpipelining to achieve higher frequency instead of adding larger buffers is advantageousfromapowerperspective. Twocasestudiescomparingtopologiesbasedonthroughputarepresented. A SystemC based simulation framework containing parameterizable routers,links, traffic generators <strong>and</strong> Sink nodes is used <strong>for</strong> <strong>NoC</strong> exploration.Organization of the ChapterRest of the chapter is organized as follows. A few router modelling, <strong>design</strong> space exploration<strong>and</strong>powerestimationrelatedworkshavebeenintroducedinSection3.1.Adetailedliterature survey router modelling <strong>and</strong> <strong>design</strong> space exploration of <strong>NoC</strong>s had been presentedin Section 2.2 of Chapter 2. <strong>NoC</strong> exploration framework used in the trade-offstudies is described in Section 3.2. Latency, power, per<strong>for</strong>mance trade-offs, frequencyscaling <strong>and</strong> voltage scaling results <strong>for</strong> two case studies are presented in Sections 3.3 <strong>and</strong>Section 3.4. Section 3.3 presents <strong>design</strong> exploration results <strong>for</strong> 4×4 2 dimensional Mesh,a similar Torus <strong>and</strong> an equivalent Folded Torus <strong>NoC</strong>. Section 3.4 presents <strong>design</strong> explorationresults <strong>for</strong> a 16 node (4×4), Torus, Reduced Torus <strong>and</strong> a Tree based <strong>NoC</strong>. Results<strong>and</strong> findings are summarized in Section 3.5.

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