NoC design and optimization for Multi-core media processors

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CHAPTER 2. RELATED WORK 21for modelling case studies. Memory arrays, crossbars and arbiters form the basic buildingblocks of all router models using this framework. Each of these building blocks havebeen modelled in detail to estimate switching capacitance. Switching activity is estimatedbased on traffic models assuming certain arrival rates at the input ports. The power numbersfor both Alpha 21364 and Infiniband routers have been found to be matching thevendors’ estimates within a minor error margin.The high level power model presented in [86] to estimate power consumption in semiglobaland global interconnects considers switching power, power due to vias and repeaters.The high level model estimates switching power within an error of 6% with aspeedup of three-to-four orders of magnitude. Error in via power is under 3%. A segmentlength distribution model has been presented for cases where Rents rule is insufficient.The segment length distribution model has been validated by analyzing netlists of a setof complex designs.A wormhole router implementing a minimal adaptive routing algorithm with nearoptimal performance and feasible design complexity is proposed in [87]. The work alsoestimates the optimal size of FIFO in an adaptive router with fixed priority scheme. Theoptimal size of the FIFO is derived to be equal to the length of the packet in flits in thiswork.2.3.3 Complete NoC ExplorationSeveral frameworks have been proposed for complete NoC exploration[89][90][91]. Theseframeworks can be used as tools to derive a first cut analysis of effect of certain NoC configurationsat an early design phase. Such frameworks are the first steps for roadmappingfuture of on-chip networks.A technology aware NoC topology exploration tool has been presented in [89]. TheNoC exploration is optimized for energy consumption of the entire SoC. The work characterizes2D Meshes and Torii along with higher dimensions, multiple hierarchies andexpress channels, for energy spent in the network. The work presents analytical modelsbased on NoC parameters such as average hop count and average flit traversal energy to
CHAPTER 2. RELATED WORK 22predict the most energy-efficient topology for future technologies.A holistic approach to designing energy-efficient cluster interconnects has been proposedin [90]. The work uses a cycle-accurate simulator with designs of an InfiniBandArchitecture (IBA) compliant interconnect fabric. The system is modelled to compriseof switches, network interface cards and links. The study reveals that the links andswitch buffers consume the major portion of the SoC power. The work proposes dynamicvoltage scaling and dynamic link shutdown as viable methods to save power during SoCoperation. A system-level roadmapping toolchain for interconnection networks has beenpresented in [91]. The framework is titled Polaris and iterates through available NoC designsto identify a power optimal one based on network traffic, architectures and processcharacteristics.Several complete NoC simulators have been developed and are in use by the NoCresearch community[92][93][94]. The Network-on-Chip Simulator, Noxim[92], was developedat the University of Catania, Italy. Several NoC parameters such as network size,buffer size, packet size distribution, routing algorithm, selection strategy, packet injectionrate, traffic time distribution, traffic pattern, hot-spot traffic distribution can be inputto this framework. The simulator allows NoC evaluation based on throughput, flit delayand power consumption. The Nostrum NoC Simulation Environment (NNSE) [94] ispart of the Nostrum project[65] and contains a SystemC based simulator. Inputs to thissimulator are network size, topology, routing policy and traffic patterns. Based on theseconfiguration parameters a simulator is built and executed to produce a desired set ofresults in a variety of graphs.2.3.4 CMP Exploration ToolsWattchwasoneofthefirst[95]architecturallevelframeworksforanalyzingandoptimizingmicroprocessor power dissipation. Wattch was orders of magnitude faster than layoutlevelpower tools, and its accuracy was within 10% of verified industry tools on leadingedgedesigns. Wattch was an architecture-level, parameterizable, simulator frameworkthat can accurately quantify potential power consumption in microprocessors. Wattch
Page 1 and 2: NoC Design & Optimization of Multic
Page 3 and 4: Abstractiibit data bus, 4 bit label
Page 5 and 6: Abstractivinterconnect latency.Simu
Page 7 and 8: PublicationsJournals• Basavaraj T
Page 9 and 10: CONTENTSviii2.4 Summary . . . . . .
Page 11 and 12: CONTENTSxC The Flow Algorithm 155C.
Page 13 and 14: LIST OF TABLESxii5.4 Synthesis Para
Page 15 and 16: LIST OF FIGURESxiv3.16 Schematic re
Page 17 and 18: LIST OF FIGURESxviB.3 8×8 mesh use
Page 19 and 20: CHAPTER 1. INTRODUCTION 2there is a
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CHAPTER 4. TILE EXPLORATION 78Table
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CHAPTER 4. TILE EXPLORATION 82Progr
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CHAPTER 4. TILE EXPLORATION 906560F
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CHAPTER 4. TILE EXPLORATION 92Progr
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CHAPTER 4. TILE EXPLORATION 981.151
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Chapter 5Label Switched NoC - Motiv
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Chapter 6LS-NoC ManagementStreaming
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CHAPTER 6. LS-NOC MANAGEMENT 118abi
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CHAPTER 6. LS-NOC MANAGEMENT 120the
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CHAPTER 6. LS-NOC MANAGEMENT 122Tab
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CHAPTER 6. LS-NOC MANAGEMENT 124Vid
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CHAPTER 6. LS-NOC MANAGEMENT 126S0l
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CHAPTER 6. LS-NOC MANAGEMENT 128Flo
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Chapter 8Conclusion and Future Work
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CHAPTER 8. CONCLUSION AND FUTURE WO
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CHAPTER 8. CONCLUSION AND FUTURE WO
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Appendix AInterface and Outputs of
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APPENDIXA. INTERFACEANDOUTPUTSOFTHE
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Appendix BTesting & Validation of L
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APPENDIX B. TESTING & VALIDATION OF
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APPENDIX B. TESTING & VALIDATION OF
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APPENDIX C. THE FLOW ALGORITHM 156X
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APPENDIX C. THE FLOW ALGORITHM 158E
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Bibliography[1] W.J. Dally and B. T
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BIBLIOGRAPHY 162[16] C. Hilton and
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BIBLIOGRAPHY 164[32] ErnoSalminen,T
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BIBLIOGRAPHY 166[50] Erno Salminen,
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BIBLIOGRAPHY 168[66] N. Megiddo. Op
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BIBLIOGRAPHY 170[84] B.S. Landman a
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BIBLIOGRAPHY 172[101] Michael Huang
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BIBLIOGRAPHY 174[118] J Gonzlez and
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BIBLIOGRAPHY 176[133] Ron Ho, Kenne
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