NoC design and optimization for Multi-core media processors

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ContentsAbstractAcknowledgementsiv1 Introduction 11.1 Network-on-Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Switching Policies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2.1 Circuit Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2.2 Packet Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2.3 Label Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3 QoS in NoCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.4 QoS Guaranteed NoC Design . . . . . . . . . . . . . . . . . . . . . . . . . 51.5 Contributions of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . 71.5.1 Link Microarchitecture Exploration . . . . . . . . . . . . . . . . . . 71.5.2 Optimal CMP Tile Configuration . . . . . . . . . . . . . . . . . . . 81.5.3 QoS in NoCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.6 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Related Work 112.1 Traffic Engineered NoC for Streaming Applications . . . . . . . . . . . . . 112.1.1 QoS in Packet Switched Networks . . . . . . . . . . . . . . . . . . . 122.1.2 QoS in Circuit Switched Networks . . . . . . . . . . . . . . . . . . . 132.1.3 QoS by Space Division Multiplexing . . . . . . . . . . . . . . . . . . 152.1.4 Static routing in NoCs . . . . . . . . . . . . . . . . . . . . . . . . . 162.1.5 MPLS and Label Switching in NoCs . . . . . . . . . . . . . . . . . 162.1.6 Label Switched NoC . . . . . . . . . . . . . . . . . . . . . . . . . . 172.2 Link Microarchitecture and Tile Area Exploration . . . . . . . . . . . . . . 172.2.1 NoC Design Space Exploration . . . . . . . . . . . . . . . . . . . . 172.3 Simulation Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.3.1 Link Exploration Tools . . . . . . . . . . . . . . . . . . . . . . . . . 182.3.2 Router Power and Architecture Exploration Tools . . . . . . . . . . 202.3.3 Complete NoC Exploration . . . . . . . . . . . . . . . . . . . . . . 212.3.4 CMP Exploration Tools . . . . . . . . . . . . . . . . . . . . . . . . 222.3.5 Communication in CMPs - Performance Exploration . . . . . . . . 24vii
CONTENTSviii2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 Link Microarchitecture Exploration 303.1 Motivation for a Microarchitectural Exploration Framework . . . . . . . . 323.2 NoC Microarchitectural Exploration Framework . . . . . . . . . . . . . . . 333.2.1 Traffic Generation and Distribution Models . . . . . . . . . . . . . 353.2.2 Router Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373.2.3 Power Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383.3 Case Study: Mesh, Torus & Folded-Torus . . . . . . . . . . . . . . . . . . . 383.3.1 NoC Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393.3.2 Round Trip Flit Latency & NoC Throughput . . . . . . . . . . . . 403.3.3 NoC Power/Performance/Latency Tradeoffs . . . . . . . . . . . . . 423.3.4 Power-Performance Tradeoff With Frequency Scaling . . . . . . . . 463.3.5 Power-Performance Tradeoff With Voltage and Frequency Scaling . 483.4 Case Study: Torus, Reduced Torus & Tree based NoC . . . . . . . . . . . . 503.4.1 NoC Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513.4.2 NoC Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523.4.3 NoC Power/Performance/Latency Tradeoffs . . . . . . . . . . . . . 533.4.4 Power-Performance Tradeoff With Frequency Scaling . . . . . . . . 543.4.5 Power-Performance Tradeoff With Voltage and Frequency Scaling . 583.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 Tile Exploration 614.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634.2 Observations and Contributions . . . . . . . . . . . . . . . . . . . . . . . . 654.3 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654.4 Communication Time and Energy Efficiency . . . . . . . . . . . . . . . . . 674.5 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734.5.1 Experimental Methodology . . . . . . . . . . . . . . . . . . . . . . . 734.6 Effect of Link Latency on Performance of a CMP . . . . . . . . . . . . . . 804.7 Communication in CMPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824.8 Program Completion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 914.9 Ideal Interconnects, Custom Floorplanning, L2 Banks and Process Mapping 964.10 Remarks & Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995 Label Switched NoC 1005.1 Streaming Applications in Media Processors . . . . . . . . . . . . . . . . . 1025.1.1 HiperLAN/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025.1.2 Object Recognition Processor . . . . . . . . . . . . . . . . . . . . . 1035.2 LS-NoC - Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045.3 LS-NoC - The Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065.4 LS-NoC - Working . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075.5 Label Switched Router Design . . . . . . . . . . . . . . . . . . . . . . . . . 1085.5.1 Pipes & Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Page 1 and 2: NoC Design & Optimization of Multic
Page 3 and 4: Abstractiibit data bus, 4 bit label
Page 5 and 6: Abstractivinterconnect latency.Simu
Page 7: PublicationsJournals• Basavaraj T
Page 11 and 12: CONTENTSxC The Flow Algorithm 155C.
Page 13 and 14: LIST OF TABLESxii5.4 Synthesis Para
Page 15 and 16: LIST OF FIGURESxiv3.16 Schematic re
Page 17 and 18: LIST OF FIGURESxviB.3 8×8 mesh use
Page 19 and 20: CHAPTER 1. INTRODUCTION 2there is a
Page 21 and 22: CHAPTER 1. INTRODUCTION 4A few prop
Page 23 and 24: CHAPTER 1. INTRODUCTION 6Figure 1.1
Page 25 and 26: CHAPTER 1. INTRODUCTION 8link micro
Page 27 and 28: CHAPTER 1. INTRODUCTION 10identify
Page 29 and 30: CHAPTER 2. RELATED WORK 12this sect
Page 31 and 32: CHAPTER 2. RELATED WORK 14Æthereal
Page 33 and 34: CHAPTER 2. RELATED WORK 16in [64] a
Page 35 and 36: CHAPTER 2. RELATED WORK 18the overa
Page 37 and 38: CHAPTER 2. RELATED WORK 20Intacte[8
Page 39 and 40: CHAPTER 2. RELATED WORK 22predict t
Page 41 and 42: CHAPTER 2. RELATED WORK 24Sapphire[
Page 43 and 44: CHAPTER 2. RELATED WORK 26case, ban
Page 45 and 46: CHAPTER 2. RELATED WORK 28Level-2 c
Page 47 and 48: Chapter 3Link Microarchitecture Exp
Page 49 and 50: CHAPTER 3. LINK MICROARCHITECTURE E
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CHAPTER 3. LINK MICROARCHITECTURE E
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CHAPTER 4. TILE EXPLORATION 62inclu
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CHAPTER 4. TILE EXPLORATION 64Execu
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CHAPTER 4. TILE EXPLORATION 66reduc
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CHAPTER 4. TILE EXPLORATION 68laten
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CHAPTER 4. TILE EXPLORATION 70local
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CHAPTER 4. TILE EXPLORATION 72each
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CHAPTER 4. TILE EXPLORATION 74Table
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CHAPTER 4. TILE EXPLORATION 76of op
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CHAPTER 4. TILE EXPLORATION 78Table
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CHAPTER 4. TILE EXPLORATION 80FFT.
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CHAPTER 4. TILE EXPLORATION 82Progr
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CHAPTER 4. TILE EXPLORATION 84resul
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CHAPTER 4. TILE EXPLORATION 906560F
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CHAPTER 4. TILE EXPLORATION 92Progr
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CHAPTER 4. TILE EXPLORATION 964.9 I
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CHAPTER 4. TILE EXPLORATION 981.151
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Chapter 5Label Switched NoC - Motiv
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CHAPTER 5. LABEL SWITCHED NOC 102Ta
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CHAPTER 5. LABEL SWITCHED NOC 1065.
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CHAPTER 5. LABEL SWITCHED NOC 110IN
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CHAPTER 5. LABEL SWITCHED NOC 1120R
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Chapter 6LS-NoC ManagementStreaming
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CHAPTER 6. LS-NOC MANAGEMENT 118abi
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CHAPTER 6. LS-NOC MANAGEMENT 120the
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CHAPTER 6. LS-NOC MANAGEMENT 122Tab
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CHAPTER 6. LS-NOC MANAGEMENT 124Vid
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CHAPTER 6. LS-NOC MANAGEMENT 126S0l
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CHAPTER 6. LS-NOC MANAGEMENT 128Flo
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CHAPTER 7. LABEL SWITCHED NOC 132OR
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CHAPTER 7. LABEL SWITCHED NOC 136LS
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CHAPTER 7. LABEL SWITCHED NOC 138co
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Chapter 8Conclusion and Future Work
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CHAPTER 8. CONCLUSION AND FUTURE WO
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CHAPTER 8. CONCLUSION AND FUTURE WO
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Appendix AInterface and Outputs of
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APPENDIXA. INTERFACEANDOUTPUTSOFTHE
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Appendix BTesting & Validation of L
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APPENDIX B. TESTING & VALIDATION OF
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APPENDIX B. TESTING & VALIDATION OF
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APPENDIX C. THE FLOW ALGORITHM 156X
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APPENDIX C. THE FLOW ALGORITHM 158E
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Bibliography[1] W.J. Dally and B. T
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BIBLIOGRAPHY 162[16] C. Hilton and
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BIBLIOGRAPHY 164[32] ErnoSalminen,T
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BIBLIOGRAPHY 166[50] Erno Salminen,
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BIBLIOGRAPHY 168[66] N. Megiddo. Op
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BIBLIOGRAPHY 170[84] B.S. Landman a
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BIBLIOGRAPHY 172[101] Michael Huang
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BIBLIOGRAPHY 174[118] J Gonzlez and
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BIBLIOGRAPHY 176[133] Ron Ho, Kenne
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