NoC design and optimization for Multi-core media processors

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CHAPTER 1. INTRODUCTION 5be distributed over the NoC resulting in fair allocation of network resources. Networkresource guarantees, enable paths with less or no jitter while keeping network utilizationfairly high. Further, design of routers is simplified compared to conventional wormholerouters[40].1.4 QoS Guaranteed NoC DesignMedia processors with streaming traffic such as HiperLAN/2 Baseband Processors[7],Real-time Object Recognition Processors [8] and H.264 encoders[44][45] demand adequatebandwidth and bounded latencies between communicating entities. They also havewell known communication patterns and bandwidth requirements. Adequate throughput,latency and bandwidth guarantees between process blocks have to be provided for suchapplications. Nature of streaming applications in media processors and characteristics ofstreaming traffic are illustrated in Section 5.1 of Chapter 5.Guaranteeing QoS by NoCs involves guaranteeing bandwidth and throughput for connectionsand deterministic latencies in communication paths. This thesis proposes a QoSguaranteeing NoC using label switching where bandwidth can be reserved while links areshared. The traffic is engineered during route setup and it leverages advantages of bothpacket and circuit switching techniques. We propose a QoS based Label Switched NoC(LS-NoC) router design. We present a latency, power and performance optimal interconnectdesign methodology considering low level circuit and system parameters. Further,optimal tile configurations are identified using effects of application communication trafficon performance and energy in chip multiprocessors (Figure 4.2).A label switched, QoS guaranteeing NoC, that retains advantages of both packetswitched and circuit switched networks is the main focus of this thesis. Congestion freecommunication pipes are identified by a centralized Manager with complete network visibility.Label Switched NoC (LS-NoC) sets up communication channels (pipes) betweencommunicating nodes that are independent of existing pipes and are contention free at therouters. Deterministic delays and bandwidth are guaranteed in newly established pipes,taking into account established flows. Residual bandwidth in links reserved by a pipe can
CHAPTER 1. INTRODUCTION 6Figure 1.1: Design space exploration of NoCs in CMPs are closely related to link microarchitecture,router design and tile configurations.be utilized by other pipes, thus enabling sharing of physical links between pipes withoutcompromising QoS guarantees. LS-NoC provides throughput guarantees irrespective ofspatial separation of the communicating entities.Interconnect delay and power contribute significantly towards the final performanceand power numbers of a CMP[46]. Design variables for interconnect exploration includewire width, wire spacing, repeater size and spacing, degree of pipelining, supply (V dd ),threshold voltage (V th ), activity and coupling factors. A power and performance optimallink microarchitecture can be arrived at by optimizing these low level link parameters.A methodology to arrive at the optimal link configuration in terms of numberof pipeline stages (cycle latency) for a given length of link and desired operating frequencyis presented. Optimal configurations of all links in the NoC are identified and apower-performance optimal NoC thus achieved.Primary and secondary cache sizes have a major bearing on the amount of on-chipand off-chip communication in a Chip Multiprocessor (CMP). On-chip and off-chip communicationtimes have significant impact on execution time and the energy efficiency ofCMPs. From a performance point of view, cache accesses should suffer minimum delayand off-tile communication due to cache misses should be negligible. Large caches dissipatemore leakage energy and may exceed area budgets though they reduce cache missesand decrease off-tile communication. Larger caches result in longer inter-tile communicationlink lengths and latencies, thus adversely impacting communication time. Small
Page 1 and 2: NoC Design & Optimization of Multic
Page 3 and 4: Abstractiibit data bus, 4 bit label
Page 5 and 6: Abstractivinterconnect latency.Simu
Page 7 and 8: PublicationsJournals• Basavaraj T
Page 9 and 10: CONTENTSviii2.4 Summary . . . . . .
Page 11 and 12: CONTENTSxC The Flow Algorithm 155C.
Page 13 and 14: LIST OF TABLESxii5.4 Synthesis Para
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Page 19 and 20: CHAPTER 1. INTRODUCTION 2there is a
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CHAPTER 3. LINK MICROARCHITECTURE E
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CHAPTER 4. TILE EXPLORATION 62inclu
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CHAPTER 4. TILE EXPLORATION 64Execu
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CHAPTER 4. TILE EXPLORATION 68laten
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CHAPTER 4. TILE EXPLORATION 70local
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CHAPTER 4. TILE EXPLORATION 72each
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CHAPTER 4. TILE EXPLORATION 74Table
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CHAPTER 4. TILE EXPLORATION 78Table
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CHAPTER 4. TILE EXPLORATION 80FFT.
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CHAPTER 4. TILE EXPLORATION 82Progr
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CHAPTER 4. TILE EXPLORATION 906560F
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CHAPTER 4. TILE EXPLORATION 92Progr
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CHAPTER 4. TILE EXPLORATION 964.9 I
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CHAPTER 4. TILE EXPLORATION 981.151
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Chapter 5Label Switched NoC - Motiv
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CHAPTER 5. LABEL SWITCHED NOC 102Ta
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Chapter 6LS-NoC ManagementStreaming
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CHAPTER 6. LS-NOC MANAGEMENT 118abi
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CHAPTER 6. LS-NOC MANAGEMENT 120the
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CHAPTER 6. LS-NOC MANAGEMENT 122Tab
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CHAPTER 6. LS-NOC MANAGEMENT 124Vid
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CHAPTER 6. LS-NOC MANAGEMENT 126S0l
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CHAPTER 6. LS-NOC MANAGEMENT 128Flo
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CHAPTER 7. LABEL SWITCHED NOC 132OR
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CHAPTER 7. LABEL SWITCHED NOC 136LS
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CHAPTER 7. LABEL SWITCHED NOC 138co
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Chapter 8Conclusion and Future Work
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CHAPTER 8. CONCLUSION AND FUTURE WO
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CHAPTER 8. CONCLUSION AND FUTURE WO
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Appendix AInterface and Outputs of
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APPENDIXA. INTERFACEANDOUTPUTSOFTHE
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Appendix BTesting & Validation of L
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APPENDIX B. TESTING & VALIDATION OF
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APPENDIX B. TESTING & VALIDATION OF
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APPENDIX C. THE FLOW ALGORITHM 156X
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APPENDIX C. THE FLOW ALGORITHM 158E
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Bibliography[1] W.J. Dally and B. T
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BIBLIOGRAPHY 162[16] C. Hilton and
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BIBLIOGRAPHY 164[32] ErnoSalminen,T
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BIBLIOGRAPHY 166[50] Erno Salminen,
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BIBLIOGRAPHY 168[66] N. Megiddo. Op
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BIBLIOGRAPHY 170[84] B.S. Landman a
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BIBLIOGRAPHY 172[101] Michael Huang
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BIBLIOGRAPHY 174[118] J Gonzlez and
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BIBLIOGRAPHY 176[133] Ron Ho, Kenne
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NoC design and optimization for Multi-core media processors

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