NoC design and optimization for Multi-core media processors

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CHAPTER 2. RELATED WORK 15slot with all of its neighbors [57]. This method will bring down the operating speed of theNoC as the slowest router will dictate the speed of the NoC. Further, power managementtechniques such as multiple clock domains is not feasible with this approach. AElite[58]and dAElite[59] have been proposed as improved next generation Æthereal NoCs. AEliteinherits the guaranteed services model from Æthereal. To overcome the global synchronicityproblem, AElite proposes use of asynchronous and mesochronous links as a possibility.As noted in the paper[58], using mesochronous links alone may not be sufficient if routersand NIs are plesiochronous[60]. One of the drawbacks of AElite was number of slotsoccupied by the header flits. A header flit in AElite occupied one in three slots and theoverhead rises to up to 33%. dAElite circumvents the header flit overhead by routingbased on the time of packet injection and packet receiving. One of the disadvantages ofdAElite is an increase in the number of link wires, due to the configuration network andalso because of separate wires for end-to-end credit communication.The Octagon NoC[34] implements a centralized best fit scheduler to configure andmanage non-overlapping connections. The scheduler cannot establish a new connectionthrough a port if it is blocked by another connection. This results in increased connectionestablishment time at the routers and also packet losses.2.1.3 QoS by Space Division MultiplexingAs an alternative to TDM techniques, Spatial Division Multiplexing (SDM) techniquesfor QoS have been proposed in [23],[61] and [62]. SDM techniques involve sharing fractionof links between connections simultaneously based on bandwidth requirements of thecorresponding connections. An approach comparable to a static version of SDM calledLane-Division-Multiplexing has been proposed in [7]. Lane-Division-Multiplexing is basedon a reconfigurable circuit switched router composed of a crossbar and data converters.Disadvantage of the solution in [7] is that it does not support channel sharing and BEtraffic. An additional network is required for configuring the switches and for carryingthe BE traffic. Sharing a subset of wires between connections as in [63] leads to a morecomplex switch design with huge delay. SDM and TDM techniques have been combined
CHAPTER 2. RELATED WORK 16in [64] allowing for increase in number of connections supported by increasing the numberof sub-channels in the link or by increasing the number of time slots. This increases pathestablishment probability in the NoC.InSDMbasedtechniques, senderserializesdataonthewiresallocated andthereceiverdeserializes the data before forwarding to the IP block. One of the issues in SDM basedcircuits is complexity of implementation of serializers and deserializers.2.1.4 Static routing in NoCsMost NoCs use traffic oblivious static routing[51] to establish communication channelsbetween nodes. Dimension ordered routing[41][53][17][53][51][34] or routes decided at designtime[65] are not flexible and cannot circumvent congested paths. Routing in FPGAsalso present a similar scenario where routes between communicating nodes are bandwidthand latency guaranteed, but are static. These routes occupy network resources along thepath for the entire lifetime of the application. QoS is guaranteed in this case by overprovisioning resources along the route.2.1.5 MPLS and Label Switching in NoCsUse of Multi-Protocol Label Switching for QoS[38] in NoCs and advantages of identifyingcommunication channels using labels have been investigated in [39],[40]. A conventionalNoC is connected to an MPLS backbone using Label Edge Routers (LERs)[38]. TheMPLSbackboneusestrafficengineeringandprioritybasedQoSservicestocommunicationchannels identified by labels. The work is a direct mapping of the MPLS implementationin the Internet to NoCs. The router and NoC design approach is not optimized for ahardware implementation. Results from Network Simulator-2 (NS-2) are at a functionallevel and may not reflect the exact performance achievable inside a chip.Use of labels to identify communication channels instead of source and destinationidentification numbers reduces the amount of metadata transmitted in the NoC. Uniqueaddressing at source allows label reuse and enables efficient use of label space. Implementationof label based addressing in streaming applications have resulted in significant
Page 1 and 2: NoC Design & Optimization of Multic
Page 3 and 4: Abstractiibit data bus, 4 bit label
Page 5 and 6: Abstractivinterconnect latency.Simu
Page 7 and 8: PublicationsJournals• Basavaraj T
Page 9 and 10: CONTENTSviii2.4 Summary . . . . . .
Page 11 and 12: CONTENTSxC The Flow Algorithm 155C.
Page 13 and 14: LIST OF TABLESxii5.4 Synthesis Para
Page 15 and 16: LIST OF FIGURESxiv3.16 Schematic re
Page 17 and 18: LIST OF FIGURESxviB.3 8×8 mesh use
Page 19 and 20: CHAPTER 1. INTRODUCTION 2there is a
Page 21 and 22: CHAPTER 1. INTRODUCTION 4A few prop
Page 23 and 24: CHAPTER 1. INTRODUCTION 6Figure 1.1
Page 25 and 26: CHAPTER 1. INTRODUCTION 8link micro
Page 27 and 28: CHAPTER 1. INTRODUCTION 10identify
Page 29 and 30: CHAPTER 2. RELATED WORK 12this sect
Page 31: CHAPTER 2. RELATED WORK 14Æthereal
Page 35 and 36: CHAPTER 2. RELATED WORK 18the overa
Page 37 and 38: CHAPTER 2. RELATED WORK 20Intacte[8
Page 39 and 40: CHAPTER 2. RELATED WORK 22predict t
Page 41 and 42: CHAPTER 2. RELATED WORK 24Sapphire[
Page 43 and 44: CHAPTER 2. RELATED WORK 26case, ban
Page 45 and 46: CHAPTER 2. RELATED WORK 28Level-2 c
Page 47 and 48: Chapter 3Link Microarchitecture Exp
Page 49 and 50: CHAPTER 3. LINK MICROARCHITECTURE E
Page 79 and 80: CHAPTER 4. TILE EXPLORATION 62inclu
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CHAPTER 4. TILE EXPLORATION 66reduc
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CHAPTER 4. TILE EXPLORATION 68laten
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CHAPTER 4. TILE EXPLORATION 70local
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CHAPTER 4. TILE EXPLORATION 72each
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CHAPTER 4. TILE EXPLORATION 74Table
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CHAPTER 4. TILE EXPLORATION 76of op
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CHAPTER 4. TILE EXPLORATION 78Table
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CHAPTER 4. TILE EXPLORATION 80FFT.
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CHAPTER 4. TILE EXPLORATION 82Progr
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CHAPTER 4. TILE EXPLORATION 84resul
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CHAPTER 4. TILE EXPLORATION 906560F
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CHAPTER 4. TILE EXPLORATION 92Progr
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CHAPTER 4. TILE EXPLORATION 964.9 I
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CHAPTER 4. TILE EXPLORATION 981.151
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Chapter 5Label Switched NoC - Motiv
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CHAPTER 5. LABEL SWITCHED NOC 102Ta
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CHAPTER 5. LABEL SWITCHED NOC 104co
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CHAPTER 5. LABEL SWITCHED NOC 1065.
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CHAPTER 5. LABEL SWITCHED NOC 108
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CHAPTER 5. LABEL SWITCHED NOC 110IN
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CHAPTER 5. LABEL SWITCHED NOC 1120R
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Chapter 6LS-NoC ManagementStreaming
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CHAPTER 6. LS-NOC MANAGEMENT 118abi
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CHAPTER 6. LS-NOC MANAGEMENT 120the
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CHAPTER 6. LS-NOC MANAGEMENT 122Tab
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CHAPTER 6. LS-NOC MANAGEMENT 124Vid
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CHAPTER 6. LS-NOC MANAGEMENT 126S0l
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CHAPTER 6. LS-NOC MANAGEMENT 128Flo
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CHAPTER 7. LABEL SWITCHED NOC 132OR
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CHAPTER 7. LABEL SWITCHED NOC 1347.
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CHAPTER 7. LABEL SWITCHED NOC 136LS
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CHAPTER 7. LABEL SWITCHED NOC 138co
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Chapter 8Conclusion and Future Work
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CHAPTER 8. CONCLUSION AND FUTURE WO
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CHAPTER 8. CONCLUSION AND FUTURE WO
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Appendix AInterface and Outputs of
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APPENDIXA. INTERFACEANDOUTPUTSOFTHE
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Appendix BTesting & Validation of L
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APPENDIX B. TESTING & VALIDATION OF
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APPENDIX B. TESTING & VALIDATION OF
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APPENDIX C. THE FLOW ALGORITHM 156X
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APPENDIX C. THE FLOW ALGORITHM 158E
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Bibliography[1] W.J. Dally and B. T
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BIBLIOGRAPHY 162[16] C. Hilton and
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BIBLIOGRAPHY 164[32] ErnoSalminen,T
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BIBLIOGRAPHY 166[50] Erno Salminen,
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BIBLIOGRAPHY 168[66] N. Megiddo. Op
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BIBLIOGRAPHY 170[84] B.S. Landman a
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BIBLIOGRAPHY 172[101] Michael Huang
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BIBLIOGRAPHY 174[118] J Gonzlez and
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BIBLIOGRAPHY 176[133] Ron Ho, Kenne
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