NoC design and optimization for Multi-core media processors

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Chapter 1Introduction1.1 Network-on-ChipNetwork on Chips[1][2][3][4] are critical elements of modern Chip Multiprocessors (CMPs)and System on Chips (SoCs). Network on Chips (NoCs) help manage high complexity ofdesigning large chips by decoupling computation from communication. SoCs and CMPshave a multiplicity of communicating entities like programmable processing elements,hardware acceleration engines, memory blocks as well as off-chip interfaces. Using anNoC enables modular design of communicating blocks and network interfaces. NoCshelp achieve a well structured design enabling higher performance while servicing largerbandwidths compared to bus based systems[1]. Links in NoCs designed with controlledelectrical parameters can use aggressive singling circuits to reduce power and delay[9].Network resources are utilized more efficiently in NoCs as compared to global wires[10].Communication patterns between communicating entities are application dependent.As a result, NoCs are expected to cater to diverse connections varying in forms of connectivity,burstiness, latency and bandwidth requirements. NoC servicing communication requirementsin CMPs or SoCs are expected to meet Quality of Service (QoS) demands suchas maximum or average latency, typical or peak bandwidth and required throughput ofexecuting applications. Further, with power having become a serious design constraint[5],1
CHAPTER 1. INTRODUCTION 2there is a great need for designing NoC which meets the target communication requirements,while minimizing power using various strategies at architecture, microarchitectureand circuit levels of the design.1.2 Switching PoliciesSwitching policies configure paths in routers to facilitate data transfer between input andoutput ports. Programming of internal switches in routers to connect input ports to outputports and determination of when and which data units are transferred is accomplishedusing switching policies. Flow control mechanisms synchronize data transfer betweenrouter and traffic sources and between two routers. Switching policies and flow controlmechanisms influence the design of internal switches, routing and arbitration units, andthe amount of buffers in a router. The major types of switching policies are introducedhere.1.2.1 Circuit SwitchingCircuit switching is a reservation based switching policy in which network resources areallocated to a communication path before data is transferred. At the end of data transfer,reserved resources are de-allocated and are available for future circuits. As circuits areused on a reservation basis, circuit switching requires a simple router design with a fewor no buffers.Circuits are established using path identifying probe packets that reserve resourcesas they propagate towards the destination. The circuit establishment is complete afteran acknowledgment message is received by the source. Data is transferred along the circuitwithout further monitoring or control. After the transfer is complete, the circuit istorn down and resources freed using a tail packet. Popular examples of circuit switchednetworks are Autonomous Error-Tolerant Cell[11], Asynchronous SoC[12], Crossroad[13],dTDMA[14], Point to point network on real time systems[15], Programmable NoC forFPGA-based systems[16], ProtoNoC[17], Space Division Multiplexing based NoC[18],
Page 1 and 2: NoC Design & Optimization of Multic
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Chapter 5Label Switched NoC - Motiv
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Chapter 6LS-NoC ManagementStreaming
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Chapter 8Conclusion and Future Work
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Appendix AInterface and Outputs of
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Appendix BTesting & Validation of L
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APPENDIX C. THE FLOW ALGORITHM 158E
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Bibliography[1] W.J. Dally and B. T
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BIBLIOGRAPHY 162[16] C. Hilton and
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BIBLIOGRAPHY 164[32] ErnoSalminen,T
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BIBLIOGRAPHY 166[50] Erno Salminen,
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BIBLIOGRAPHY 168[66] N. Megiddo. Op
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BIBLIOGRAPHY 170[84] B.S. Landman a
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BIBLIOGRAPHY 172[101] Michael Huang
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BIBLIOGRAPHY 174[118] J Gonzlez and
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BIBLIOGRAPHY 176[133] Ron Ho, Kenne
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NoC design and optimization for Multi-core media processors

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