NoC design and optimization for Multi-core media processors

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CHAPTER 2. RELATED WORK 25Figure 2.1: Floorplan used in estimating wire lengths. Wire lengths estimated from thesefloorplans are used as input to Intacte to arrive at a power optimal configuration andlatencyinclockcycles. HorizontalR-R:Linkbetweenneighboringroutersinthehorizontaldirection, Vertical R-R: Link between neighbouring routers in the vertical direction.Cache Based Microarchitectural TechniquesStridedprefetching[106]hasbeencomparedwithblockmigrationandonchiptransmissionlines to manage on-chip wire delay in CMP caches to improve performance. Work in [106]combines block migration strategies, transmission line caches and stride-based hardwareto reduce cache based communication latencies in CMPs. Dynamic Non-Uniform CacheArchitecture (DNUCA)[107] uses block migration techniques to reduce cache latencies.Block migration involves moving frequently accessed blocks in the cache into banks withlower latencies. On chip transmission lines are used to provide low latency to all banks inTransmission Line Caches[108]. Around 40%-60% of L2 cache hits are satisfied in centralbanks in CMPs with shared L2 rendering block migration ineffective. TLCs suffer frombandwidth contention reducing its advantage.Communication energy and delay can be minimized by migrating frequently accessedcachelinestobanksclosesttotheaccessingprocessors[109][110][111]. Non-UniformCacheArchitectures (NUCAs) with policies allow important cache lines to migrate toward theprocessor within the same level of the cache have been proposed in [109][110]. The cachearchitecture proposed in [109][110] shows that a dynamic NUCA structure achieves higherIPC than a traditional Uniform Cache Architecture (UCA) when maintaining the samesize and manufacturing technology. D-NUCA mapping policy attempts to provide fastestbankaccessto all banksetsby sharingtheclosest banksamong multiplebanksets. In this
CHAPTER 2. RELATED WORK 26case, banksinthecachearen-waysetassociativeiftheyshareasinglebank. Theproposedmethod results in low latency access, technology scalability, performance stability due toflattening of memory hierarchy.Work in [111] analyses the influence on performance by network routers in NUCAcaches. Specifically the work looks at cut-through latency and buffering capacity of networkroutersconnectingthecachecontrollertodifferentsub-banksinNUCAcaches.Theyconclude that the effect of cut-through latency on the performance of the caches is highand modest buffering is sufficient to achieve a good performance level. The work proposesa clustered NUCA organization that places an upper limit on the average numberof hops experienced by cache accesses. This method simplifies router implementation,scales better with cut-through latencies and is more effective compared to hybrid networksolutions.Compiler Assisted TechniquesInstruction steering [112] and instruction replication[113] coupled with clustering havebeen researched as an effective technique to reduce the impact of wire delays. In Clusteredsuperscalar microarchitecture, critical components are partitioned into smaller processingunits called clusters. The centralized instruction window is replaced with multiple smallerwindows. Simpler smaller blocks allow clusters to operate at higher clock speeds at betterenergy efficiency and are scalable. However clustering trades-off IPC to score on theseparameters. Clusters reduce the impact of wire delays by reducing the complexity andpower consumption in clusters. Instruction steering involves assigning instructions toclusters in such a manner that workload is balanced and off-cluster communication isreduced. Work in [112] reduces communication during steering. The work proposes anAccurate Rebalancing technique to offload processes from the most utilized processor tothe lesser utilized processors such that intra-cluster communication is minimal. Topologyaware steering has also been proposed as method to decrease latency between source anddestination clusters.
Page 1 and 2: NoC Design & Optimization of Multic
Page 3 and 4: Abstractiibit data bus, 4 bit label
Page 5 and 6: Abstractivinterconnect latency.Simu
Page 7 and 8: PublicationsJournals• Basavaraj T
Page 9 and 10: CONTENTSviii2.4 Summary . . . . . .
Page 11 and 12: CONTENTSxC The Flow Algorithm 155C.
Page 13 and 14: LIST OF TABLESxii5.4 Synthesis Para
Page 15 and 16: LIST OF FIGURESxiv3.16 Schematic re
Page 17 and 18: LIST OF FIGURESxviB.3 8×8 mesh use
Page 19 and 20: CHAPTER 1. INTRODUCTION 2there is a
Page 21 and 22: CHAPTER 1. INTRODUCTION 4A few prop
Page 23 and 24: CHAPTER 1. INTRODUCTION 6Figure 1.1
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Page 29 and 30: CHAPTER 2. RELATED WORK 12this sect
Page 31 and 32: CHAPTER 2. RELATED WORK 14Æthereal
Page 33 and 34: CHAPTER 2. RELATED WORK 16in [64] a
Page 35 and 36: CHAPTER 2. RELATED WORK 18the overa
Page 37 and 38: CHAPTER 2. RELATED WORK 20Intacte[8
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CHAPTER 4. TILE EXPLORATION 76of op
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CHAPTER 4. TILE EXPLORATION 78Table
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CHAPTER 4. TILE EXPLORATION 82Progr
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CHAPTER 4. TILE EXPLORATION 906560F
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CHAPTER 4. TILE EXPLORATION 92Progr
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CHAPTER 4. TILE EXPLORATION 964.9 I
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CHAPTER 4. TILE EXPLORATION 981.151
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Chapter 5Label Switched NoC - Motiv
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Chapter 6LS-NoC ManagementStreaming
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CHAPTER 6. LS-NOC MANAGEMENT 118abi
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CHAPTER 6. LS-NOC MANAGEMENT 120the
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CHAPTER 6. LS-NOC MANAGEMENT 122Tab
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CHAPTER 6. LS-NOC MANAGEMENT 124Vid
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CHAPTER 6. LS-NOC MANAGEMENT 126S0l
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CHAPTER 6. LS-NOC MANAGEMENT 128Flo
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Chapter 8Conclusion and Future Work
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CHAPTER 8. CONCLUSION AND FUTURE WO
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CHAPTER 8. CONCLUSION AND FUTURE WO
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Appendix AInterface and Outputs of
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APPENDIXA. INTERFACEANDOUTPUTSOFTHE
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Appendix BTesting & Validation of L
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APPENDIX B. TESTING & VALIDATION OF
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APPENDIX B. TESTING & VALIDATION OF
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APPENDIX C. THE FLOW ALGORITHM 156X
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APPENDIX C. THE FLOW ALGORITHM 158E
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Bibliography[1] W.J. Dally and B. T
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BIBLIOGRAPHY 162[16] C. Hilton and
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BIBLIOGRAPHY 164[32] ErnoSalminen,T
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BIBLIOGRAPHY 166[50] Erno Salminen,
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BIBLIOGRAPHY 168[66] N. Megiddo. Op
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BIBLIOGRAPHY 170[84] B.S. Landman a
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BIBLIOGRAPHY 172[101] Michael Huang
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BIBLIOGRAPHY 174[118] J Gonzlez and
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BIBLIOGRAPHY 176[133] Ron Ho, Kenne
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