NoC design and optimization for Multi-core media processors

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AcknowledgementsI thank my advisor, Prof. Bharadwaj Amrutur for his invaluable guidance throughout myPh.D. I thank all of you who have shared many precious moments with me and enrichedmy journey through life.v
PublicationsJournals• Basavaraj Talwar and Bharadwaj Amrutur, “Traffic Engineered NoC for StreamingApplications”, Microprocessors and Microsystems, 37(2013), 333-344.Conferences• Basavaraj Talwar and Bharadwaj Amrutur, “A System-C based MicroarchitecturalExploration Framework for Latency, Power and Performance Trade-offs of On-ChipInterconnection Networks”, First International Workshop on Network on Chip Architectures,Nov. 2008.• Basavaraj Talwar, Shailesh Kulkarni and Bharadwaj Amrutur, “Latency, Powerand Performance Trade-offs in Network-on-Chips by Link Microarchitecture Exploration”,22 nd Intl. Conference on VLSI Design, Jan. 2009.vi
Page 1 and 2: NoC Design & Optimization of Multic
Page 3 and 4: Abstractiibit data bus, 4 bit label
Page 5: Abstractivinterconnect latency.Simu
Page 9 and 10: CONTENTSviii2.4 Summary . . . . . .
Page 11 and 12: CONTENTSxC The Flow Algorithm 155C.
Page 13 and 14: LIST OF TABLESxii5.4 Synthesis Para
Page 15 and 16: LIST OF FIGURESxiv3.16 Schematic re
Page 17 and 18: LIST OF FIGURESxviB.3 8×8 mesh use
Page 19 and 20: CHAPTER 1. INTRODUCTION 2there is a
Page 21 and 22: CHAPTER 1. INTRODUCTION 4A few prop
Page 23 and 24: CHAPTER 1. INTRODUCTION 6Figure 1.1
Page 25 and 26: CHAPTER 1. INTRODUCTION 8link micro
Page 27 and 28: CHAPTER 1. INTRODUCTION 10identify
Page 29 and 30: CHAPTER 2. RELATED WORK 12this sect
Page 31 and 32: CHAPTER 2. RELATED WORK 14Æthereal
Page 33 and 34: CHAPTER 2. RELATED WORK 16in [64] a
Page 35 and 36: CHAPTER 2. RELATED WORK 18the overa
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Page 39 and 40: CHAPTER 2. RELATED WORK 22predict t
Page 41 and 42: CHAPTER 2. RELATED WORK 24Sapphire[
Page 43 and 44: CHAPTER 2. RELATED WORK 26case, ban
Page 45 and 46: CHAPTER 2. RELATED WORK 28Level-2 c
Page 47 and 48: Chapter 3Link Microarchitecture Exp
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CHAPTER 3. LINK MICROARCHITECTURE E
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CHAPTER 4. TILE EXPLORATION 62inclu
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CHAPTER 4. TILE EXPLORATION 64Execu
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CHAPTER 4. TILE EXPLORATION 66reduc
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CHAPTER 4. TILE EXPLORATION 68laten
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CHAPTER 4. TILE EXPLORATION 70local
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CHAPTER 4. TILE EXPLORATION 72each
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CHAPTER 4. TILE EXPLORATION 74Table
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CHAPTER 4. TILE EXPLORATION 76of op
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CHAPTER 4. TILE EXPLORATION 78Table
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CHAPTER 4. TILE EXPLORATION 80FFT.
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CHAPTER 4. TILE EXPLORATION 82Progr
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CHAPTER 4. TILE EXPLORATION 84resul
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CHAPTER 4. TILE EXPLORATION 906560F
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CHAPTER 4. TILE EXPLORATION 92Progr
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CHAPTER 4. TILE EXPLORATION 964.9 I
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CHAPTER 4. TILE EXPLORATION 981.151
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Chapter 5Label Switched NoC - Motiv
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CHAPTER 5. LABEL SWITCHED NOC 102Ta
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CHAPTER 5. LABEL SWITCHED NOC 104co
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CHAPTER 5. LABEL SWITCHED NOC 1065.
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CHAPTER 5. LABEL SWITCHED NOC 108
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CHAPTER 5. LABEL SWITCHED NOC 110IN
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CHAPTER 5. LABEL SWITCHED NOC 1120R
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Chapter 6LS-NoC ManagementStreaming
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CHAPTER 6. LS-NOC MANAGEMENT 118abi
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CHAPTER 6. LS-NOC MANAGEMENT 120the
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CHAPTER 6. LS-NOC MANAGEMENT 122Tab
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CHAPTER 6. LS-NOC MANAGEMENT 124Vid
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CHAPTER 6. LS-NOC MANAGEMENT 126S0l
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CHAPTER 6. LS-NOC MANAGEMENT 128Flo
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CHAPTER 7. LABEL SWITCHED NOC 132OR
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CHAPTER 7. LABEL SWITCHED NOC 1347.
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CHAPTER 7. LABEL SWITCHED NOC 136LS
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CHAPTER 7. LABEL SWITCHED NOC 138co
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Chapter 8Conclusion and Future Work
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CHAPTER 8. CONCLUSION AND FUTURE WO
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CHAPTER 8. CONCLUSION AND FUTURE WO
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Appendix AInterface and Outputs of
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APPENDIXA. INTERFACEANDOUTPUTSOFTHE
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Appendix BTesting & Validation of L
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APPENDIX B. TESTING & VALIDATION OF
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APPENDIX B. TESTING & VALIDATION OF
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APPENDIX C. THE FLOW ALGORITHM 156X
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APPENDIX C. THE FLOW ALGORITHM 158E
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Bibliography[1] W.J. Dally and B. T
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BIBLIOGRAPHY 162[16] C. Hilton and
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BIBLIOGRAPHY 164[32] ErnoSalminen,T
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BIBLIOGRAPHY 166[50] Erno Salminen,
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BIBLIOGRAPHY 168[66] N. Megiddo. Op
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BIBLIOGRAPHY 170[84] B.S. Landman a
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BIBLIOGRAPHY 172[101] Michael Huang
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BIBLIOGRAPHY 174[118] J Gonzlez and
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BIBLIOGRAPHY 176[133] Ron Ho, Kenne
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NoC design and optimization for Multi-core media processors

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