Chapter 4 PA-RISC Computer Systems - OpenPA.net

Early PA-RISC Systems
4.2 Early PA-RISC Systems
Information on these very early models and their details is sometimes quite incoherent. This includes
HP documentation (both sales and technical), which not always describe the processor and system
features of these computers coherently. In some cases, the system type was deduced — from supplied
system block diagrams together with MIPS “benchmarks.” Computers names and model numbers were
also compiled from various sources and may be not completely correct. (See Note 1)
4.2.1 840: First PA-RISC Server, TS-1 (TTL) (See Note 2)
The first commercial PA-RISC product appeared in 1986 with the HP 9000/840 (Indigo) computer,
based on a six-board TTL implementation of the 32-bit PA-RISC 1.0 architecture, TS-1, running at
8 MHz. The TTL boards measure 8.4×11.3″ , SRAMs/PALs and about 150 ICs each. The TS-1 boards
implement the processor pipeline, a 4096-entry TLB and 128 KB (L1) cache, divided into 64 KB for
each data and instruction.
Two main buses are used in the I/O system:
1. Central Bus (CTB — also called MidBus) connects the processor to the main memory and the
secondary I/O bus (see below). CTB is 32-bit wide and has a clock speed of 8 MHz, with a
sustained transfer rate of 20 MB/s. Seven slots for general purpose I/O cards are available.
2. Channel I/O (CIO) is the central device I/O bus. Up to three CIO buses (also called CIBs) are supported
in a single 9000/840 computer. (Others mention only one CIO channel on the 9000/840
— all three channels apparently were reserved for the very similar HP 3000/930.) CIO/CIB is
16-bit wide and achieves a transfer rate of 5 MB/s with a clock speed of 4 MHz. Seven (shared)
I/O slots are available. Supported devices on CIO include HP-IB (Hewlett-Packard Interface-Bus,
commonly used for instrumentation and measurement devices) and networking adapters.
Seven shared slots for I/O and memory are available, for up to 112 MB of RAM (7×16 MB; 2-16 MB
memory modules were supported). The optional graphics adapter used one I/O and one memory slot,
reducing the maximum RAM to 96 MB. Included by default into the system is a separate Floating
Point Coprocessor (FPC) board. The 840 could be upgraded via a CPU board swap to 825, 835 or
845s retaining the case and memory and I/O boards.
It achieved about 4.5 MIPS and ran HP-UX version 1.0 (heavily BSD-based) up until version 10.01 (the
pre-Y2k release). Storage and media devices were attached to the HP-IB bus, SCSI was only later (and
with newer boot ROMs) available.
4.2.2 825, 835 and 850: NS-1 (NMOS)
One year later, 1987, first systems with 32-bit PA-RISC 1.0 processors implemented in NMOS-III logic,
the PA-RISC NS-1, appeared: (See Note 3)
HP 9000/825 FireFox (also HP 9000/825S):
� 25 MHz NS-1 processor on two boards
� 16 KB cache
� 2048-entry TLB
� CTBs run at 8.33 MHz
143