Chapter 4 PA-RISC Computer Systems - OpenPA.net

PA-RISC Processors PA-7100/PA-7150 (PCX-T)
2.2.5 PA-7100/PA-7150 (PCX-T)
Overview
The PA-7100 was the first PA-RISC CPU to integrate the ALU and FPU on a single die, saving board
space and lowering production cost. It was introduced in 1992, with the enhanced PA-7150 being
added in 1994. The design of the integer units is close to the PA-7000, which was modified to scale
to higher frequencies; the (previously external) FPU was newly designed, taking about one third of the
transistor count. The link between the PA-7100 and its instruction cache was doubled compared to the
PA-7000, which enables the CPU to fetch multiple consecutive instructions and simultaneously dispatch
them to independent integer and floating point units. The PA-7100 is a superscalar processor that is
able to issue two separate instructions at a time.
SMP systems can be built with two alternative strategies: either two PA-7100s attach via a shared PBus
to one Memory and I/O Controller (Viper) to which the system bus and memory separately attach; or
each PA-7100 is attached to its own MIOC, which in turn is attached to a shared memory and I/O bus
with the other PA-7100/MIOCs.
The PA-7150 is a PA-7100 with tweaks to the core and cache subsystem to allow clock frequencies up
to 125 MHz.
Details
� PA-RISC version 1.1b 32-bit
� Two functional units: 1 integer ALU, 1 Floating Point unit
� 2-way superscalar
� SMP-capable
� CPU, FPU, MMU and cache controller on one chip, memory and I/O controller (Viper MIOC)
off-chip
� Five-stage pipeline
� Pipeline store technique for reduction of penalty for execution of any store to data cache
� Stall-on-use mechanism for parallel procession of instruction streams and cache misses
� 3-instruction queue
� Hardware TLB miss handler
� Hardware static branch support
� I/D cache bypass (7150)
� Off-chip L1 caches up to 1 MB I and 2 MB D realized in asynchronous standard SRAMs
� I/D caches are both 64-bit per access, direct mapped, parity protected and cycled at CPU clock
� Caches are attached directly to the CPU
� Caches are software accessible
� Caches are virtually indexed and physically tagged to minimize latency
� 120-entry fully associative TLB
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