Chapter 4 PA-RISC Computer Systems - OpenPA.net

PA-RISC Chipsets Prelude (Stretch)
Used in
� C100, C110 C160, C180, C200, C240, C360
� D-Class
� J200, J210, J210XC, J280, J282, J2240
� K-Class
References
� A New Memory System Design for Commercial and Technical Computing Products 83 (.pdf)
Thomas R. Hotchkiss, Norman D. Marschke, and Richard M. McClosky (Februar 1996: Hewlett-
Packard Journal)
� And cf. the references of U2/UTurn above
2.5.17 Prelude (Stretch)
Prelude is the memory controller of systems with the Stretch chipset and connects the main memory
via four memory buses to two system buses. The main buses are in fact Itanium/Merced buses in
preparation of the HP shift from PA-RISC to Itanium. Systems with Stretch theoretically could have
been upgraded to Itanium processors, which however never realized.
Details
� Two system buses, each 2.1 GB/s peak with 4.3 GB/s aggregate
� Up to four memory buses, each 2.1 GB/s peak with 8.6 GB/s aggregate to the memory
� Both memory and system buses are Itanium/Merced buses at 133 MHz DDR with 64-bit width,
ECC-protected
� System main buses connect to the CPU bridges (DEW) and I/O controllers (IKE)
� SDRAM memory
� Up to 16 pairs of DIMMs supported
� Prelude consists of three VLSI chips: one address controller and two data controllers; each data
controller drives two multiplexed 64-bit memory buses
Used in
� L1500 (rp5430), L3000 (rp5470)
� N4000 (rp7400)
83 http://www.hpl.hp.com/hpjournal/96feb/feb96a5.pdf
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