Chapter 4 PA-RISC Computer Systems - OpenPA.net

PA-RISC Buses Runway
Runway CPU attachments
The PA-7200, PA-8000 and PA-8200 processors with the Runway bus use split I/O and memory controllers
— the U2/UTurn I/O Adapters (IOAs) and MMC/SMC memory controllers with each what can
be called “frontends” and “backends” , with the former interfacing to the CPU and its processor bus
and the latter attaching the frontend to customized bus attachments on their external side. This allowed
HP to use the frontend parts of these chipsets with a variety of different system design which
only required modified backend parts for new memory or I/O technologies.
1. Runway is the main processor and memory bus
� 1-4 CPUs attach to Runway with 64-bit, parity-protected
� SMP-capable
2. MMC is the main memory controller which attaches to Runway
� Master Memory Controller (MMC)
� Attaches to Runway with 64-bit (with example of 120 MHz at a data rate of 960 MB/s peak)
� Memory attaches to MMC via slave Memory Controllers (SMC) and Data Multiplexers,
128-bit 60 MHz data (ECC) and 39-bit 60 MHz address buses
3. U2/UTurn I/O adapters attach the main I/O bus and system to the Runway processor bus
� Attach to Runway with 64-bit
� Two I/O adapters (IOAs) per U2/UTurn chip
� Maximum data rate depends on Runway clock with 120 MHz and 64-bit: 960 MB/s
4. GSC+, the main system bus, attach to the U2/UTurn IOAs
� Attaches via 32-bit at a fraction of Runway/IOA clock, mostly 40 MHz
� PA-7300LC systems use the extended GSC version
5. I/O adapters and slots attach to GSC+
� LASI chipset
� Video adapters
� I/O slots extend GSC
� Bus adapters, including EISA, VME and PCI, attach to GSC+
Runway+/Runway DDR CPU attachments
The PA-8500, PA-8600, PA-8700 processors use an advanced version of the Runway system bus with
increased data rate and utilized different I/O and memory controllers, with most using the Astro chipset
(IOMMU) and few servers the sophisticated Stretch and Cell chipsets.
Described below is the common configuration with Astro chipset — for the Stretch/Cell bus attachments
see their entries at the Chipset page.
1. Runway+/Runway DDR is the main processor and memory bus
� 1-4 CPUs attach to Runway with 64-bit, parity-protected
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