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Chapter 4 PA-RISC Computer Systems - OpenPA.net

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HP 9000 rp4410 & rp4440<br />

4.38 HP 9000 rp4410 & rp4440<br />

4.38.1 Overview<br />

Time of introduction: 2004<br />

The rp4400 series rp4410 and rp4440 servers are, as their smaller rp3410 and rp3440 siblings, one of<br />

the last <strong>PA</strong>-<strong>RISC</strong>-based HP servers. They are driven by up to two (rp4410) or four (rp4440) dual-core<br />

<strong>PA</strong>-8800 Mako or <strong>PA</strong>-8900 processors. The rp4400s are based around the Itanium 2/IA64-capable HP<br />

zx1 chipset, and technically very similar to the rp3400’s architecture. The systems can be rack-mounted<br />

(4U) or used stand-alone.<br />

List price at time of introduction: US $21,000 for a (single-CPU, dual-core) rp4440.<br />

4.38.2 Internals<br />

CPU<br />

rp4410<br />

� 1 or 2 dual-core <strong>PA</strong>-8800 900 MHz-1.0 GHz with 1.5 MB/1.5 MB on-chip I/D L1 cache and<br />

32 MB off-chip L2 cache each<br />

or<br />

� 1 or 2 dual-core <strong>PA</strong>-8900 800 MHz-1.1 GHz with 1.5 MB/1.5 MB on-chip I/D L1 cache and<br />

64 MB off-chip L2 cache each<br />

rp4440<br />

� 1, 2 or 4 dual-core <strong>PA</strong>-8800 900 MHz-1.0 GHz with 1.5 MB/1.5 MB on-chip I/D L1 cache and<br />

32 MB off-chip L2 cache each<br />

or<br />

� 1, 2 or 4 dual-core <strong>PA</strong>-8900 800 MHz-1.1 GHz with 1.5 MB/1.5 MB on-chip I/D L1 cache and<br />

64 MB off-chip L2 cache each<br />

It is probably possible to upgrade the CPUs to Itanium 2/IA64 processors.<br />

Chipset<br />

The systems are based on HP’s zx1 chipset, which consists of three main components — the MIO (memory<br />

and I/O controller), the IOAs (I/O adapters) and the SMEs (scalable memory expanders):<br />

� Pluto zx1 MIO (memory and I/O controller) is the main chipset controller and connects the three<br />

central system buses:<br />

1. Processor bus (6.4 GB/s) for one (rp4410) or two (rp4440) dual-CPU modules<br />

2. Two independent memory buses (each 6.4 GB/s)<br />

3. Eight I/O channels (aggregate 4.0 GB/s, via the IOAs, see below)<br />

� Six zx1 SMEs (scalable memory expanders) attach to two independent zx1 memory buses (each<br />

6.4 GB/s)<br />

288

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